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PCD5096 bảng dữ liệu(PDF) 19 Page - NXP Semiconductors |
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PCD5096 bảng dữ liệu(HTML) 19 Page - NXP Semiconductors |
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19 / 52 page ![]() 1997 Jan 22 19 Philips Semiconductors Preliminary specification Universal codec PCD5096 8.3.7 CONTROL REGISTER 5 (CR5) CR5 controls the general purpose I/O pin IO0. Table 23 Control Register 5 (address 7DH) Table 24 Description of CR5 bits Note 1. Depending on the DSP program, the contents of CR5 might be overwritten by the DSP as soon as the reset is inactive. 8.3.8 CONTROL REGISTER 6 (CR6) CR6 controls the general purpose I/O pin IO1. Table 25 Control Register 6 (address 7EH) Table 26 Description of CR6 bits Note 1. Depending on the DSP program, the contents CR6 might be overwritten by the DSP as soon as the reset is inactive. 10 IODIR0 IO0 BIT SYMBOL DESCRIPTION 1 IODIR0 Direction control for IO0. If IODIR0 = 1, then IO0 is an input. If IODIR0 = 0, then IO0 is an output. Input during and after reset; see note 1. 0 IO0 State of IO0 10 IODIR1 IO1 BIT SYMBOL DESCRIPTION 1 IODIR1 Direction control for IO1. If IODIR1 = 1, then IO1 is an input. If IODIR1 = 0, then IO1 is an output. Input during and after reset; see note 1. 0 IO1 State of IO1 |
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