VT8235 datasheet(64/145 Pages) VIA

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VT8235 V-Link South Bridge

Revision 1.22 October 24, 2002

-58-

Device 16 Function 3 USB 2.0 EHCI Registers

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Device 16 Function 3 Registers - USB 2.0 EHCI

This Enhanced Serial Bus host controller interface is fully

compatible with EHCI specification v1.0. There are two sets

of software accessible registers: PCI configuration registers

and USB I/O registers. The PCI configuration registers are

located in the Device 16 Function 3 PCI configuration space

of the VT8235. The USB I/O registers are defined in EHCI

specification v1.0. The registers in this function control USB

2.0 functions (see functions 0-2 for USB 1.1 UHCI control).

PCI Configuration Space Header

Offset 1-0 - Vendor ID (1106h)......................................... RO

7-0

Vendor ID

................. (1106h = VIA Technologies)

Offset 3-2 - Device ID (3104h) .......................................... RO

7-0

Device ID

(3104h = VT8235 USB 2.0 EHCI

Controller)

Offset 5-4 - Command (0000h) .........................................RW

15-8 Reserved

........................................ always reads 0

Address Stepping

...................... default=0 (disabled)

Reserved

(parity error response) ................. fixed at 0

Reserved

(VGA palette snoop) ................... fixed at 0

Memory Write and Invalidate

. default=0 (disabled)

Reserved

(special cycle monitoring) ........... fixed at 0

Bus Master

............................... default=0 (disabled)

Memory Space

........................... default=0 (disabled)

I/O Space

............................... default=0 (disabled)

Offset 7-6 - Status (0210h) .............................................RWC

Reserved

(detected parity error).......... always reads 0

Signaled System Error

............................... default=0

Received Master Abort

.............................. default=0

Received Target Abort

............................... default=0

Signaled Target Abort

............................... default=0

10-9 DEVSEL# Timing

00 Fast

01 Medium ......................................default (fixed)

10 Slow

11 Reserved

8-0

Reserved

.............................. fixed 10h (PCI PMI)

Offset 8 - Revision ID (nnh).............................................. RO

7-0

Silicon Revision Code

Offset 9 - Programming Interface (20h) .......................... RO

Offset A - Sub Class Code (03h=USB Controller) .......... RO

Offset B - Base Class Code (0Ch=Serial Bus Controller)RO

Offset C – Cache Line Size (10h) ..................................... RW

Offset D - Latency Timer (16h) ....................................... RW

Offset 13-10 – EHCI Memory Mapped I/O Base Addr . RW

31-8 EHCI Memory Mapped I/O Registers Base

Address.

Memory Address for the base of the USB

2.0 EHCI I/O Register block, corresponding to

AD[31:8]

7-3

Reserved

........................................always reads 0

2-1

Memory Mapping

.....reads 00b for 32-bit addressing

Reserved

........................................always reads 0

Offset 2D-2C - Sub Vendor ID (1106h).......................... RO†

Offset 2F-2E - Sub Device ID (3104h) ............................ RO†

† RW if Rx42[4] = 1.

Offset 34 - Power Management Capabilities (80h) ........ RW

Offset 3C - Interrupt Line (00h) ...................................... RW

7-4

Reserved

........................................always reads 0

3-0

USB Interrupt Routing

0000 Disabled ................................................. default

0001 IRQ1

0010 Reserved

0011 IRQ3

0100 IRQ4

0101 IRQ5

0110 IRQ6

0111 IRQ7

1000 IRQ8

1001 IRQ9

1010 IRQ10

1011 IRQ11

1100 IRQ12

1101 IRQ13

1110 IRQ14

1111 Disabled

Offset 3D - Interrupt Pin (04h) ......................................... RO

7-0

Interrupt Pin

..........................default = 04h (INTD#)

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