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VT8235 bảng dữ liệu(PDF) 21 Page - VIA Technologies, Inc.

tên linh kiện VT8235
Giải thích chi tiết về linh kiện  V-LINK CLIENT HIGHLY INTEGRATED SOUTH BRIDGE
PDF  145 Pages
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nhà sản xuất  VIA [VIA Technologies, Inc.]
Trang chủ  https://www.viatech.com/en/
Logo VIA - VIA Technologies, Inc.

VT8235 bảng dữ liệu(HTML) 21 Page - VIA Technologies, Inc.

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VT8235 V-Link South Bridge
Revision 1.22 October 24, 2002
-15-
Pin Descriptions
Urpu‚y‚tvr†ÃDp
XrÃ8‚rp‡
UltraDMA-133 / 100 / 66 / 33 Enhanced IDE Interface (continued)
Signal Name
Pin #
I/O
Signal Description
PDCS1#
V24
O
Primary Master Chip Select.
This signal corresponds to CS1FX# on
the primary IDE connector.
PDCS3#
W24
O
Primary Slave Chip Select.
This signal corresponds to CS3FX# on
the primary IDE connector.
SDCS1#
/ strap
AC23
O
Secondary Master Chip Select.
This signal corresponds to CS17X#
on the secondary IDE connector.
Strap low (resistor to ground) to
enable serial EEPROM interface via the MII bus (this disables the
EExx pins).
This pin has an internal pullup to default to serial
EEPROM interface via the Eexx pins.
SDCS3#
/ strap
AD23
O
Secondary Slave Chip Select.
This signal corresponds to CS37X# on
the secondary IDE connector. Strap information is communicated to
the north bridge via VAD[7].
PDA[2-0]
V26, V25, Y23
O
Primary Disk Address.
PDA[2:0] are used to indicate which byte in
either the ATA command block or control block is being accessed.
SDA[2-0]
/ strap
AF23, AC22, AE23
O
Secondary Disk Address.
SDA[2:0] are used to indicate which byte in
either the ATA command block or control block is being accessed.
Strap information is communicated to the north bridge via VAD[6:4].
PDD[15-0]
(see pin list)
IO
Primary Disk Data.
SDD[15-0]
/ SA[15-0]
(see pin list)
IO / IO
Secondary Disk Data.
PDCOMP
W23
I
Primary Disk Compensation.
SDCOMP
AC15
I
Secondary Disk Compensation.
Serial IRQ
Signal Name
Pin #
I/O
Signal Description
SERIRQ
AE10
I
Serial IRQ.
This pin has an internal pull-up resistor.
AC97 Audio / Modem Interface
Signal Name
Pin # I/O Signal Description
ACRST#
R3
O
AC97 Reset.
ACBTCK
T3
I
AC97 Bit Clock.
ACSYNC
T1
O
AC97 Sync.
ACSDO
U1
O
AC97 Serial Data Out.
ACSDIN0
(VSUS33)†
T2
I
AC97 Serial Data In 0.
ACSDIN1
(VSUS33)†
U3
I
AC97 Serial Data In 1.
ACSDIN2
/ GPIO20 / PCS0#
U2
I
AC97 Serial Data In 2.
RxE4[6]=0,E5[1]=0, PMIO Rx4C[20]=1
ACSDIN3
/ GPIO21 / PCS1# / SLPBTN#
V1
I
AC97 Serial Data In 3.
RxE4[6]=0,E5[2]=0, PMIO Rx4C[21]=1
†The supply voltage for ACSDIN0-1 is VSUS33 so these inputs can support wake-up on modem ring.



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