CDC706PW datasheet(32/41 Pages) TI

32 / 41 page

www.ti.com

100

120

140

160

180

200

220

240

260

280

300

100

120

140

160

180

200

220

240

260

280

300

320

340

360

T =25 C,

=3.3V,

Mdiv=4,

Ndiv=15,

P div=3

High-Speed Mode

>180MHz

FrequencyRange

VCO

forHigh-SpeedMode

forNormal-SpeedMode

VCO FrequencyRange

Normal-SpeedMode

<200MHz

fVCO − MHzSetPoint

Cross Coupling, Spur Suppression and Noise Rejection

CDC706

SCAS829A – SEPTEMBER 2006 – REVISED MARCH 2007

Figure 29. Period Jitter vs fVCO for Normal-Speed Mode and High-Speed Mode

The TI Pro Clock software automatically calculates the PLL parameter for jitter-optimized performance.

Cross-Coupling in ICs occurs through interactions between several parts of the chip such as between output

stages, metal lines, bond wires, substrate, etc. The coupling can be capacitive, inductive and resistive (ohmic)

induced by output switching, leakage current, ground bouncing, power supply transients, etc.

The CDC706 is designed in BiCMOS process technology incorporating silicon-germanium (SiGe) technology.

This process gives excellent performance in linearity, low power consumption, best-in-class noise performance

and very good isolation characteristic between the on-chip components.

The good isolation was a major criteria to use BiCMOS process as it minimizes the coupling effect. Even if all

three PLLs are active and all outputs are on, the noise suppression is clearly above 50 dB. Figure 30 and

Figure 31 show an example of noise coupling, spur-suppression, and power supply noise rejection of CDC706.

Die respective measurement conditions are shown in Figure 30 and Figure 31.

Submit Documentation Feedback

CDC706PW bảng dữ liệu(PDF) 32 Page - Texas Instruments

CDC706PW bảng dữ liệu(HTML) 32 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

bảng dữ liệu tải về

Link URL