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CDC706PW bảng dữ liệu(PDF) 13 Page - Texas Instruments

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tên linh kiện CDC706PW
Giải thích chi tiết về linh kiện  PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER
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CDC706PW bảng dữ liệu(HTML) 13 Page - Texas Instruments

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Block Read Programming Sequence
P
S
P
SCLK
SDATA
A
Bit 7 (MSB)
Bit 6
Bit 0 (LSB)
th(SDATA)
tsu(SDATA)
tsu(START)
t(BUS)
th(START)
tr(SM)
tr(SM)
tf(SM)
tf(SM)
tW(SCLH)
tW(SCLL)
tsu(STOP)
VIH(SM)
VIL(SM)
VIH(SM)
VIL(SM)
SMBus Hardware Interface
9
10
SDATA
SCLK
SMBHost
CDC706
CBUS
CBUS
RP
RP
CDC706
SCAS829A – SEPTEMBER 2006 – REVISED MARCH 2007
1
7
1
1
8
1
1
7
1
1
S
Slave Address
Wr
A
CommandCode
A
Sr
Slave Address
Rd
A
8
1
8
1
8
1
1
Byte Count N
A
Data Byte 0
A
- - - - -
Data Byte N–1
A
P
Figure 10. Block Read Protocol
Figure 11. Timing Diagram Serial Control Interface
The following diagram shows how the CDC706 clock synthesizer is connected to the SMBus. Note that the
current through the pullup resistors (Rp) must meet the SMBus specifications (min 100 µA, max 350 µA). If the
CDC706 is not connected to SMBus, the SDATA and SCLK inputs have to be connected with 10 k
Ω resistors to
VCC to avoid floating input conditions.
Figure 12. SMBus Hardware Interface
13
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