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Performance Data: Output Skew, Jitter, Cross Coupling, Noise Rejection (Spur-Suppression),

Output Skew

Jitter Performance

CDC706

SCAS829A – SEPTEMBER 2006 – REVISED MARCH 2007

and Phase Noise

Skew is an important parameter for clock distribution circuits. It is defined as the time difference between outputs

low-to-high transitions over the entire range of supply voltages, operating temperature and output voltage swing.

Table 5. Output Skew

PARAMETER

TYP

MAX

UNIT

2.5 V

130

250

ps

3.3 V

130

200

ps

Jitter is a major parameter for PLL-based clock driver circuits. This becomes important as speed increases and

timing budget decreases. The PLL and internal circuits of CDC706 are designed for lowest jitter. The

peak-to-peak period jitter is only 60 ps (typical). Table 6 gives the peak-to-peak and rms deviation of

cycle-to-cycle jitter, period jitter and phase jitter as taken during characterization.

Table 6. Jitter Performance of CDC706

PARAMETER

UNIT

Peak-Peak

rms

Peak-Peak

rms

(one sigma)

(one sigma)

50 MHz

55

–

75

–

ps

133 MHz

50

–

85

–

245.76 MHz

45

–

60

–

50 MHz

60

4

76

7

ps

133 MHz

55

5

84

11

245.76 MHz

55

5

72

8

50 MHz

730

90

840

115

ps

133 MHz

930

130

1310

175

245.76 MHz

720

90

930

125

(1)

10000 cycles.

Figure 26, Figure 27, and Figure 28 show the relationship between cycle-to-cycle jitter, period jitter, and phase

jitter over 10000 samples. The jitter varies with a smaller or wider sample window. The cycle-to-cycle jitter and

period jitter show the measured value whereas the phase jitter is the accumulated period jitter.

sample of adjacent cycle pairs. Cycle-to-cycle jitter will never be greater than the period jitter. It is also known as

adjacent cycle jitter.

29

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