AD9271 datasheet(9/58 Pages) AD

9 / 58 page

Preliminary Technical Data

AD9271

Rev. PrA | Page 9 of 58

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, CWVDD = 3.3 V, 400 m V p-p differential input, 1.0 V internal ADC reference, AIN = −0.5 dBFS, unless

otherwise noted.

Table 3.

Parameter1

Temp

Min

Typ

Max

Unit

CLOCK2

Maximum Clock Rate

Full

MSPS

Minimum Clock Rate

Full

MSPS

Clock Pulse Width High (tEH)

Full

10.0

Clock Pulse Width Low (tEL)

Full

10.0

OUTPUT PARAMETERS2, 3

Propagation Delay (tPD)

Full

1.5

2.3

3.1

Rise Time (tR) (20% to 80%)

Full

300

Fall Time (tF) (20% to 80%)

Full

300

FCO Propagation Delay (tFCO)

Full

1.5

2.3

3.1

DCO Propagation Delay (tCPD)4

Full

tFCO +

(tSAMPLE/24)

DCO to Data Delay (tDATA)4

Full

(tSAMPLE/24) − 300

(tSAMPLE/24)

(tSAMPLE/24) + 300

DCO to FCO Delay (tFRAME)4

Full

(tSAMPLE/24) − 300

(tSAMPLE/24)

(tSAMPLE/24) + 300

Data-to-Data Skew

(tDATA-MAX − tDATA-MIN)

Full

±50

±200

Wake-Up Time (Standby)

25°C

600

Wake-Up Time (Power-Down)

25°C

375

μs

Pipeline Latency

Full

CLK

cycles

APERTURE

Aperture Uncertainty (Jitter)

25°C

ps rms

1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2 Can be adjusted via the SPI interface.

3 Measurements were made using a part soldered to FR4 material.

4 tSAMPLE/24 is based on the number of bits divided by 2, because the delays are based on half duty cycles.

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