AD9271 datasheet(39/58 Pages) AD

39 / 58 page

Preliminary Technical Data

AD9271

Rev. PrA | Page 39 of 58

Addr.

(Hex)

Parameter Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

Default

Value

(Hex)

Default Notes/

Comments

1010 = 1× sync

1011 = one bit high

1100 = mixed bit frequency

(format determined by output_mode)

Flex_channel_input

Filter cutoff frequency control

0000 = 0.7 × 1/3 × fSAMPLE

0001 = 0.8 × 1/3 × fSAMPLE

0010 = 0.9 × 1/3 × fSAMPLE

0011 = 1.0 × 1/3 × fSAMPLE

0100 = 1.1 × 1/3 × fSAMPLE

0101 = 1.2 × 1/3 × fSAMPLE

0110 = 1.3 × 1/3 × fSAMPLE

0x30

Antialiasing filter

cutoff (global)

Flex_offset

6-bit LNA offset adjustment

Table = TBD

0x20

LNA force offset

correction

(local)

Flex_gain

LNA gain

00 = 5×

01 = 6×

10 = 8×

0x01

LNA gain

adjustment

(global)

output_mode

0 = LVDS

ANSI

(default)

1 = LVDS

low power,

(IEEE

1596.3

similar)

Output

invert

1 = on

0 = off

(default)

00 = offset binary

(default)

01 = twos

complement

0x00

Configures the

outputs and the

format of the data.

output_adjust

Output driver

termination

00 = none (default)

01 = 200 Ω

10 = 100 Ω

11 = 100 Ω

DCO

and FCO

2× drive

strength

1 = on

0 = off

(default)

0x00

Determines LVDS

or other output

properties.

Primarily functions

to set the LVDS

span and

common-mode

levels in place of

an external

resistor.

output_phase

0011 = output clock phase adjust

(0000 through 1010)

(Default: 180° relative to DATA edge)

0000 = 0° relative to DATA edge

0001 = 60° relative to DATA edge

0010 = 120° relative to DATA edge

0011 = 180° relative to DATA edge

0100 = 240° relative to DATA edge

0101 = 300° relative to DATA edge

0110 = 360° relative to DATA edge

0111 = 420° relative to DATA edge

1000 = 480° relative to DATA edge

1001 = 540° relative to DATA edge

1010 = 600° relative to DATA edge

1011 to 1111 = 660° relative to DATA edge

0x03

On devices that

utilize global

clock divide,

determines which

phase of the

divider output is

used to supply

the output clock.

Internal latching

is unaffected.

user_patt1_lsb

0x00

User-defined

pattern, 1 LSB

(global).

user_patt1_msb

B15

B14

B13

B12

B11

B10

0x00

User-defined

pattern, 1 MSB

(global).

user_patt2_lsb

0x00

User-defined

pattern, 2 LSB.

(global)

user_patt2_msb

B15

B14

B13

B12

B11

B10

0x00

User-defined

pattern, 2 MSB

(global).

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