CS8405A-CS datasheet(29/37 Pages) CIRRUS

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CS8405A

DS469F2

11.PIN DESCRIPTION - HARDWARE MODE

COPY / C

ORIG

VL2+

VL4+

EMPH

TXP

SFMT0

TXN

SFMT1

H/S

VD+

VL+

DGND4

DGND

DGND3

OMCK

RST

VL3+

APMS

AUDIO

TCBLD

ILRCK

ISCLK

CEN

SDIN

TCBL

821

VD+

6 Digital Power (Input) - Digital core power supply. Typically +5.0 V.

VL+

VL2+

VL3+

VL4+

Logic Power

(Input) - Input/Output power supply. Typically +3.3 V or +5.0 V. All VL+ pins must be

at the same voltage.

DGND

DGND3

DGND4

Digital Ground

(Input) - Ground for the digital section.

RST

9 Reset (Input) - When RST is low, the CS8405A enters a low power mode and all internal states are

reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks

are stable in frequency and phase. This is particularly true in hardware mode with multiple CS8405A

devices, where synchronization between devices is important.

H/S

24 Hardware/Software Control Mode Select (Input) -Determines the method of controlling the opera-

tion of the CS8405A, and the method of accessing CS and U data. In software mode, device control

and CS and U data access is primarily through the control port, using a microcontroller. Hardware

mode provides an alternate mode of operation, and access to CS and U data is provided by dedi-

cated pins. This pin should be permanently tied to VL+ or DGND.

TXN

TXP

Differential Line Drivers

(Output) - These pins transmit biphase encoded data. The drivers are

pulled low while the CS8405A is in the reset state.

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