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CS8405A-CS bảng dữ liệu(PDF) 16 Page - Cirrus Logic

tên linh kiện CS8405A-CS
Giải thích chi tiết về linh kiện  96 kHz Digital Audio Interface Transmitter
PDF  37 Pages
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nhà sản xuất  CIRRUS [Cirrus Logic]
Trang chủ  http://www.cirrus.com
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CS8405A-CS bảng dữ liệu(HTML) 16 Page - Cirrus Logic

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CS8405A
16
DS469F2
of the chip address, and should be connected to
VL+ or DGND as desired. The upper four bits of the
seven-bit address field are fixed at 0010. To com-
municate with a CS8405A, the chip address field,
which is the first byte sent to the CS8405A, should
match 0010 followed by the settings of AD2, AD1,
and AD0. The eighth bit of the address is the R/W
bit. If the operation is a write, the next byte is the
Memory Address Pointer (MAP) which selects the
register to be read or written. If the operation is a
read, the contents of the register pointed to by the
MAP will be output. Setting the auto increment bit
in MAP allows successive reads or writes of con-
secutive registers. Each byte is separated by an
acknowledge bit, ACK, which is output from the
CS8405A after each input byte is read. The ACK
bit is input to the CS8405A from the microcontroller
after each transmitted byte. I²C mode is supported
only with VL+ = 5.0 V.
6.3
Interrupts
The CS8405A has a comprehensive interrupt ca-
pability. The INT output pin is intended to drive the
interrupt input pin on the host microcontroller. The
INT pin may be set to be active low, active high or
active low with no active pull-up transistor. This last
mode is used for active low, wired-OR hook-ups,
with multiple peripherals connected to the micro-
controller interrupt input pin.
Many conditions can cause an interrupt, as listed in
the interrupt status register descriptions. Each
source may be masked off by a bit in the mask reg-
isters. In addition, each source may be set to rising
edge, falling edge, or level sensitive. Combined
with the option of level sensitive or edge sensitive
modes within the microcontroller, many different
set-ups are possible, depending on the needs of
the equipment designer.
SD A
SC L
00 10
AD 2-0
R/W
Start
AC K
D ATA7-0
AC K
DATA7 -0
AC K
Stop
No te 2
Note 1
Note 3
Figure 9. Control Port Timing in
I²C Mode
Notes: 1. AD2, AD1, and AD0 are determined by the state of the corresponding pins.
2. If operation is a write, this byte contains the Memory Address Pointer, MAP.
3. If operation is a read, the last bit of the read should be NACK (high).



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