CS8405A-CS datasheet(6/37 Pages) CIRRUS

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CS8405A

DS469F2

SWITCHING CHARACTERISTICS

(Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF)

SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS

(Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF)

Notes: 6. The active edge of ISCLK is programmable.

7. The polarity of ILRCK is programmable.

8. No more than 128 SCLK per frame.

9. Prevents the previous ISCLK edge from being interpreted as the first one after ILRCK has changed.

10. This setup time ensures that this ISCLK edge is interpreted as the first one after ILRCK has changed

Parameter

Symbol

Min

Typ

Max

Units

RST pin Low Pulse Width

200

µs

OMCK Frequency for OMCK = 512 * Fso

4.1

55.3

MHz

OMCK Low and High Width for OMCK = 512 * Fso

7.2

OMCK Frequency for OMCK = 384 * Fso

3.1

41.5

MHz

OMCK Low and High Width for OMCK = 384 * Fso

10.8

OMCK Frequency for OMCK = 256 * Fso

2.0

27.7

MHz

OMCK Low and High Width for OMCK = 256 * Fso

14.4

Frame Rate

8.0

108.0

kHz

AES3 Transmitter Output Jitter

Parameter

Symbol

Min

Typ

Max

Units

SDIN Setup Time Before ISCLK Active Edge

(Note 6)

tds

SDIN Hold Time After ISCLK Active Edge

(Note 6)

tdh

Master Mode

OMCK to ISCLK active edge delay

(Note 6)

tsmd

OMCK to ILRCK delay

(Note 7)

tlmd

ISCLK and ILRCK Duty Cycle

Slave Mode

ISCLK Period

(Note 8)

tsckw

ISCLK Input Low Width

tsckl

ISCLK Input High Width

tsckh

ISCLK Active Edge to ILRCK Edge

(Note 6,7,9)

tlrckd

ILRCK Edge Setup Before ISCLK Active Edge (Note 6,7,10)

tlrcks

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