TMS320F datasheet(67/389 Pages) TI

67 / 389 page

Program-Address Generation

5-3

Program Control

Table 5–1. Program-Address Generation Summary

Operation

Program-Address Source

Sequential operation

PC (contains program address +1)

Dummy cycle

PAR (contains program address)

Return from subroutine

Top of the stack (TOS)

Return from table move or block move

Microstack (MSTACK)

Branch or call to address specified in

instruction

Branch or call instruction by way of the

program read bus (PRDB)

Branch or call to address specified in

lower half of the accumulator

Low accumulator by way of the data

read bus (DRDB)

Branch to interrupt service routine

Interrupt vector location by way of the

program read bus (PRDB)

The ’C24x program-address generation logic uses the following hardware:

- Program counter (PC). The ’C24x has a 16-bit program counter (PC) that

addresses internal and external program memory when fetching instruc-

tions.

- Program address register (PAR). The PAR drives the program address

bus (PAB). The PAB is a 16-bit bus that provides program addresses for

both reads and writes.

- Stack. The program-address generation logic includes a 16-bit-wide, 8-

level hardware stack for storing up to eight return addresses. In addition,

you can use the stack for temporary storage.

- Microstack (MSTACK). Occasionally, the program-address generation

logic uses the 16-bit-wide, 1-level MSTACK to store one return address.

- Repeat counter (RPTC). The 16-bit RPTC is used with the repeat (RPT)

instruction to determine how many times the instruction following RPT is

repeated.

TMS320F bảng dữ liệu(PDF) 67 Page - Texas Instruments