TMS320F datasheet(55/389 Pages) TI

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Central Arithmetic Logic Section

4-11

Central Processing Unit

4.3.3

Output Data-Scaling Shifter

The output data-scaling shifter (output shifter) has a 32-bit input connected to

the 32-bit output of the accumulator and a 16-bit output connected to the data

bus. The shifter copies all 32 bits of the accumulator and then performs a left

shift on its content; it can be shifted from zero to seven bits, as specified in the

corresponding store instruction. The upper word (SACH instruction) or lower

word (SACL instruction) of the shifter is then stored to data memory. The con-

tent of the accumulator remains unchanged.

When the output shifter performs the shift, the MSBs are lost and the LSBs are

zero filled. Figure 4–7 shows an example in which the accumulator value is

shifted left by four bits and the shifted high word is stored to data memory.

Figure 4–8 shows the same accumulator value shifted left by six bits and the

shifted low word stored.

Figure 4–7. Shifting and Storing the High Word of the Accumulator

Data-memory

location

0 0 F 0

F 0 A 1

0 F 0 F

0 A 1 0

Output shifter

(left shift by 4 bits)

Accumulator

0 F 0 F

Figure 4–8. Shifting and Storing the Low Word of the Accumulator

Data-memory

location

0 0 F 0

F 0 A 1

3 C 3 C

2 8 4 0

Output shifter

(left shift by 6 bits)

Accumulator

2 8 4 0

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