MSP430F14X datasheet(27/83 Pages) TI

27 / 83 page

MSP430F149, MSP430F148, MSP430F147

MSP430F1491, MSP430F1481, MSP430F1471

MSP430F135, MSP430F133

www.ti.com

SLAS272H – JULY 2000 – REVISED MAY 2018

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MSP430F135 MSP430F133

Specifications

(1)

The leakage current is defined in the leakage current table.

(2)

The analog input voltage range must be within the selected reference voltage range VR+ to VR− for valid conversion results.

(3)

The internal reference supply current is not included in current consumption parameter IADC12.

(4)

The internal reference current is supplied through the AVCC terminal. Consumption is independent of the ADC12ON control bit, unless a

conversion is active. The REFON bit enables to settle the built-in reference before starting a conversion.

(5)

Not production tested, limits verified by design.

5.23 12-Bit ADC, Power Supply and Input Range Conditions

over recommended operating supply voltage and free-air temperature (unless otherwise noted)

(1)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

AVCC

Analog supply voltage

AVCC and DVCC are connected together,

AVSS and DVSS are connected together,

V(AVSS) = V(DVSS) = 0 V

2.2

3.6

V(P6.x/Ax)

Analog input voltage (2)

All P6.0/A0 to P6.7/A7 terminals, analog

inputs selected in ADC12MCTLx register

and P6Sel.x = 1,

≤ x ≤ 7, V(AVSS) ≤ V(P6.x/Ax) ≤ V(AVCC)

VAVCC

IADC12

ADC operating supply current

into AVCC terminal

(3)

fADC12CLK = 5.0 MHz,

ADC12ON = 1, REFON = 0,

SHT0 = 0, SHT1 = 0, ADC12DIV = 0

2.2 V

0.65

1.3

3 V

0.8

1.6

IREF+

REF operating supply current

into AVCC terminal

(4)

fADC12CLK = 5.0 MHz, ADC12ON = 0,

REFON = 1, REF2_5V = 1

3 V

0.5

0.8

fADC12CLK = 5.0 MHz, ADC12ON = 0,

REFON = 1, REF2_5V = 0

2.2 V

0.5

0.8

3 V

0.5

0.8

Input capacitance(5)

Only one P6.x/Ax terminal can be selected

at one time

2.2 V

Input MUX ON resistance(5)

0 V

≤ VAx ≤ VAVCC

3 V

2000

(1)

The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the

dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the

recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.

(2)

The accuracy requirements limit the minimum positive external reference voltage. Lower reference voltage levels may be applied with

reduced accuracy requirements

(3)

The accuracy requirements limit the maximum negative external reference voltage. Higher reference voltage levels may be applied with

reduced accuracy requirements.

(4)

The accuracy requirements limit the minimum external differential reference voltage. Lower differential reference voltage levels may be

applied with reduced accuracy requirements.

5.24 12-Bit ADC, External Reference

over recommended operating supply voltage and free-air temperature (unless otherwise noted)

(1)

PARAMETER

TEST CONDITIONS

VCC

MIN

MAX

UNIT

VVeREF+

Positive external reference input voltage

VVeREF+ > VVREF-/VeREF-

(2)

1.4

VAVCC

VVREF-/VeREF-

Negative external reference input voltage

VVeREF+ > VVREF-/VeREF-

(3)

1.2

VVeREF+ −

VVREF-/VeREF-

Differential external reference input voltage VVeREF+ > VVREF-/VeREF-

(4)

1.4

VAVCC

IVeREF+

Static input current, VeREF+

0 V

≤ VVeREF+ ≤ VAVCC

2.2 V, 3 V

±1

µA

IVREF-/VeREF-

Static input current, VeREF

−

0 V

≤ VVeREF− ≤ VAVCC

2.2 V, 3 V

±1

µA

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