MSP430F14X datasheet(19/83 Pages) TI

19 / 83 page

MSP430F149, MSP430F148, MSP430F147

MSP430F1491, MSP430F1481, MSP430F1471

MSP430F135, MSP430F133

www.ti.com

SLAS272H – JULY 2000 – REVISED MAY 2018

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Product Folder Links: MSP430F149 MSP430F148 MSP430F147 MSP430F1491 MSP430F1481 MSP430F1471

MSP430F135 MSP430F133

Specifications

Inputs – Px.y, TAx, TBx (continued)

over recommended operating supply voltage and free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

MIN

MAX

UNIT

f(TAint),

f(TBint)

Timer_A or Timer_B clock frequency

SMCLK or ACLK signal selected

2.2 V

MHz

3 V

(1)

The leakage current is measured with VSS or VCC applied to the corresponding pin, unless otherwise noted.

(2)

The port pin must be set as input, and the optional pullup or pulldown resistor must be disabled.

5.9

Leakage Current

over recommended operating supply voltage and free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

MIN

MAX

UNIT

Ilkg(P1.x)

Leakage current(1)

Port P1

V(P1.x)

(2)

2.2 V, 3 V

±50

Ilkg(P2.x)

Port P2

V(P2.3), V(P2.4)

(2)

±50

Ilkg(P6.x)

Port P6

V(P6.x)

(2)

±50

(1)

The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, must not exceed ±6 mA to hold the maximum voltage drop

specified.

(2)

The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, must not exceed ±24 mA to hold the maximum voltage drop

specified.

5.10 Outputs – Ports P1, P2, P3, P4, P5, and P6

over recommended operating supply voltage and free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

MIN

MAX

UNIT

VOH

High-level output voltage

I(OHmax) = –1 mA

(1)

2.2 V

VCC – 0.25

VCC

I(OHmax) = –6 mA

(2)

VCC – 0.60

VCC

I(OHmax) = 1 mA

(1)

3 V

VCC – 0.25

VCC

I(OHmax) = –6 mA

(2)

VCC – 0.60

VCC

VOL

Low-level output voltage

I(OLmax) = 1.5 mA

(1)

2.2 V

VSS VSS + 0.25

I(OLmax) = 6 mA

(2)

VSS

VSS + 0.6

I(OLmax) = 1.5 mA

(1)

3 V

VSS VSS + 0.25

I(OLmax) = 6 mA

(2)

VSS

VSS + 0.6

(1)

The limits of the system clock MCLK must be met; the MCLK frequency must not exceed the limits. MCLK and SMCLK frequencies can

be different.

5.11 Output Frequency

over recommended operating supply voltage and free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

fTAx

Timer_A or Timer_B output

frequency

Internal clock source, SMCLK signal applied(1),

TA0 to TA2, TB0 to TB6, CL = 20 pF

fSYSTEM

MHz

fACLK

Clock output frequency

Measured at P5.6/ACLK

CL = 20 pF

fSYSTEM

MHz

fMCLK

Measured at P5.4/MCLK

fSYSTEM

fSMCLK

Measured at P5.5/SMCLK

fSYSTEM

tXdc

Duty cycle of output

frequency

Measured at P2.0/ACLK,

CL = 20 pF,

VCC = 2.2 V or 3 V

fACLK = fLFXT1 = fXT1

40%

60%

fACLK = fLFXT1 = fLF

30%

70%

fACLK = fLFXT1/n

50%

Measured at P1 4/SMCLK,

CL = 20 pF,

VCC = 2.2 V or 3 V

fSMCLK = fLFXT1 = fXT1

40%

60%

fSMCLK = fLFXT1 = fLF

35%

65%

fSMCLK = fLFXT1/n

50% –

15 ns

50%

50% +

15 ns

fSMCLK = fDCOCLK

50% –

15 ns

50%

50% +

15 ns

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