AT83SND2CMP3B datasheet(156/241 Pages) ATMEL

156 / 241 page

156

4341F–MP3–03/06

AT8xC51SND2C/MP3B

19. Synchronous Peripheral Interface

The AT8xC51SND2C implements a Synchronous Peripheral Interface with master and slave

modes capability.

Figure 19-1 shows an SPI bus configuration using the AT8xC51SND2C as master connected to

slave peripherals while Figure 19-2 shows an SPI bus configuration using the AT8xC51SND2C

as slave of an other master.

The bus is made of three wires connecting all the devices together:

•

Master Output Slave Input (MOSI): it is used to transfer data in series from the master to a

slave.

It is driven by the master.

•

Master Input Slave Output (MISO): it is used to transfer data in series from a slave to the

master.

It is driven by the selected slave.

•

Serial Clock (SCK): it is used to synchronize the data transmission both in and out the

devices through their MOSI and MISO lines. It is driven by the master for eight clock cycles

which allows to exchange one Byte on the serial lines.

Each slave peripheral is selected by one Slave Select pin (SS). If there is only one slave, it may

be continuously selected with SS tied to a low level. Otherwise, the AT8xC51SND2C may select

each device by software through port pins (Pn.x). Special care should be taken not to select 2

slaves at the same time to avoid bus conflicts.

Figure 19-1.

Typical Master SPI Bus Configuration

Figure 19-2.

Typical Slave SPI Bus Configuration

AT8xC51SND2C

DataFlash 1

MISO

MOSI

SCK

P4.0

P4.1

P4.2

Pn.z

Pn.y

Pn.x

SCK

DataFlash 2

SCK

LCD

Controller

SCK

MASTER

Slave 1

MISO

MOSI

SCK

SSn

SS1

SS0

SCK

Slave 2

SCK

AT8xC51SND2C

Slave n

MISO MOSI SCK

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