AT83SND2CMP3B datasheet(124/241 Pages) ATMEL

124 / 241 page

124

4341F–MP3–03/06

AT8xC51SND2C/MP3B

Table 16-6.

USBIEN Register

USBIEN (S:BEh) – USB Global Interrupt Enable Register

Reset Value = 0001 0000b

Table 16-7.

UEPNUM Register

UEPNUM (S:C7h) – USB Endpoint Number

Reset Value = 0000 0000b

543

210

EWUPCPU

EEORINT

ESOFINT

ESPINT

Bit Number

Bit

Mnemonic

Description

7 - 6

Reserved

The value read from these bits is always 0. Do not set these bits.

5EWUPCPU

Wake Up CPU Interrupt Enable Bit

Set to enable the Wake Up CPU interrupt.

Clear to disable the Wake Up CPU interrupt.

EEOFINT

End Of Reset Interrupt Enable Bit

Set to enable the End Of Reset interrupt. This bit is set after reset.

Clear to disable End Of Reset interrupt.

ESOFINT

Start Of Frame Interrupt Enable Bit

Set to enable the SOF interrupt.

Clear to disable the SOF interrupt.

2 - 1

Reserved

The value read from these bits is always 0. Do not set these bits.

ESPINT

Suspend Interrupt Enable Bit

Set to enable Suspend interrupt.

Clear to disable Suspend interrupt.

543

210

---

EPNUM1

EPNUM0

Bit Number

Bit

Mnemonic

Description

7 - 2

Reserved

The value read from these bits is always 0. Do not set these bits.

1 - 0

EPNUM1:0

Endpoint Number Bits

Set this field with the number of the endpoint which should be accessed when reading or

writing to registers UEPSTAX, UEPDATX, UBYCTX or UEPCONX.

AT83SND2CMP3B bảng dữ liệu(PDF) 124 Page - ATMEL Corporation

AT83SND2CMP3B bảng dữ liệu(HTML) 124 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL