WM9705SEFTSLASHV datasheet(28/55 Pages) WOLFSON

28 / 55 page

WM9705

Production Data

PD Rev 4.4 August 2006

A new audio input frame begins with a low to high transition of SYNC as shown in Figure 15.

SYNC is synchronous to the rising edge of BITCLK. On the immediately following falling edge of

BITCLK, the WM9705 samples the assertion of SYNC. This falling edge marks the time when

both sides of AC-link are aware of the start of a new audio frame. On the next rising edge of

BITCLK, the AC’97 controller transitions SDATAIN into the first bit position of slot 0 (valid frame

bit). Each new bit position is presented to AC-link on a rising edge of BITCLK, and subsequently

sampled by the AC’97 controller on the following falling edge of BITCLK. This sequence ensures

that data transitions and subsequent sample points for both incoming and outgoing data streams

are time aligned.

SDATAIN’s composite stream is MSB justified (MSB first) with all non-valid bit positions (for

assigned and/or unassigned time slots) stuffed with 0’s by the WM9705. SDATAIN is sampled on

the falling edges of BITCLK.

SLOT 1: STATUS ADDRESS PORT

The status port is used to monitor status for the WM9705 functions including, but not limited to,

mixer settings, and power management.

Audio input frame slot 1 echoes the control register index, for historical reference, for the data to

be returned in slot 2. (Assuming that slots 1 and 2 had been tagged valid by the WM9705 during

slot 0).

Bit (19)

RESERVED (stuffed with 0s)

Bit (18:12)

Control register index (echo of register index for which data is

being returned)

Bit (11:2)

Variable Sample Rate SLOTREQ bits

Bit[1:0]

RESERVED (stuffed with 0s)

Table 5 Status Address Port Bit Assignments

The first bit (MSB) generated by the WM9705 is always stuffed with a 0. The following 7 bit

positions communicate the associated control register address. The next 10 bits support the

AC'97 Rev 2.2 variable sample rate signaling protocol and the trailing 2 bit positions are stuffed

with 0s by the codec.

SLOT 2: STATUS DATA PORT

The status data port delivers 16-bit control register read data.

Bit (19:4)

Control register read data (stuffed with 0s if tagged invalid by

WM9705)

Bit (3:0)

RESERVED (stuffed with 0s)

Table 6 Status Data Port Bit Assignments

If slot 2 is tagged invalid by the WM9705, then the entire slot will be stuffed with 0s by the

WM9705.

SLOTS 3 AND 4: PCM RECORD LEFT AND RIGHT CHANNELS

Audio input frame slots 3 and 4 are the left and right channel outputs of the WM9705’s audio

ADC. Note that this data may alternatively be mapped onto slots 6 and 9, or 7 and 8 under control

of the mapping bits ASS[1:0] in register 5Ch. The WM9705 sends out its ADC output data (MSB

first), and stuffs any trailing non-valid bit positions with 0s to fill out its 20-bit time slot.

SLOT 5: OPTIONAL MODEM LINE ADC

This slot is not supported by WM9705 in AC’97 compliant mode - this may be determined by the

AC’97 controller interrogating the WM9705 Reset Register, 00h. However, Pen ADC data may be

output in this slot, selected by SLT[2:0] in register 76h.

SLOTS 6 AND 9:

These data slots may be utilised by the WM9705 to output audio data under control of the

mapping bits ASS[1:0] in register 5Ch, allowing implementation of multi-channel systems. These

slots may also be used to output Pen ADC data.

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