WM9705 datasheet(20/55 Pages) WOLFSON

20 / 55 page

WM9705

Production Data

PD Rev 4.4 August 2006

enhancement applied. It can also be bypassed if desired. This function is enabled by setting the

bit POP in Register 20h.

VARIABLE SAMPLE RATE SUPPORT

The DACs and ADCs on this device support all the recommended sample rates specified in the

Intel AC’97 rev2.1 and rev2.2 specifications for audio rates. The default rate is 48ks/s. If

alternative rates are selected and variable rate audio is enabled (Register 2Ah, bit 0), the AC’97

interface continues to run at 48k words per second, but data is transferred across the link in

bursts such that the net sample rate selected is achieved. It is up to the AC’97 Revision 2.1/2

compliant controller to ensure that data is supplied to the AC link, and received from the AC link,

at the appropriate rate.

Variable rates are selected by writing to registers 2Ch (DAC) and 32h (ADC). ADC and DAC rates

may be set independently, with left and right channels always at the same rate. Note that register

2Ch should only be written to when the DAC is powered ON, similarly register 32h should only be

written to when the ADC is powered ON (see register 26h for power control). The device supports

on demand sampling. That is, when the DAC signal processing circuits need another sample, a

sample request is sent to the controller which must respond with a data sample in the next frame

it sends. For example, if a rate of 24ks/s is selected, on average the device will request a sample

from the controller every other frame, for each of the stereo DACs. Note that if an unsupported

rate is written to one of the rate registers, the rate will default to the nearest rate supported. The

The WM9705 clocks will scale automatically dependent upon the MCLK frequency, where MCLK

is not equal to 24.576MHz. With a 24MHz clock the BCLK frequency expected will be 12MHz and

the sampling frequency (SYNC0 expected is BCLK/256 = 46.875kHz.

AUDIO

SAMPLE RATE

CONTROL VALUE

D15-D0

8000

1F40

11025

2B11

16000

3E80

22050

5622

32000

7D000

44100

AC44

48000

BB80

Table 1 Variable Sample Rates Supported

SPDIF OR I

2S DIGITAL AUDIO DATA OUTPUT

The WM9705 SPDIF output may be enabled in hardware by holding pin 44 (SPEN) high when

RESETB is taken high, or by writing to the SPDIF control bit in register 2Ah. If SPDIF pin 48 is

pulled high at start-up by a weak pull-up (e.g. 100k), then SPDIF capability bit in register 28h is

set to ‘0’, i.e. no SPDIF capability. This allows for stuffing options, so that when SPDIF external

components are not provided, the driver will see ‘no SPDIF capability’ and ‘grey out’ the relevant

boxes in the control panel.

Additionally the digital audio may be output in I

2S format using pin 44 (SPEN) as the data output,

and outputting a frame clock or LRCLK onto pin 43. The data is clocked onto pin 44 using the

regular BITCLK at 256fs, which would also then be used as the MCLK if the data is taken to an

external DAC. Operation in this mode is selected by setting bit I

2S in register 5Ch. A 64fs bitclk is

also available and can be output on SPDIF by setting bit I2S64 in register 74h. Note that I

operation is only supported for 48ks/s operation. Hardware selection of SPDIF operation by

pulling pin SPEN ‘hi’ is compatible with I

2S operation, provided a weak pull-up (circa 100k) was

used to hold SPEN high at start-up. The SPEN pin becomes I

2S data output pin when I2S is

enabled, and the weak pull-up on this pin is overdriven.

For both SPDIF and I

2S modes the data that is output may be sent from the WM9705 via the AC

link in the same slots as normal DAC data or may be sent in different slots. The output slots that

contain the SPDIF/I

2S data are selected by bits SPSA[1:0] in register 2Ah. WM9705 is compliant

with AC’97 rev2.2 specification with regard to slot mapping; therefore the default mode of

operation is to output SPDIF or I

2S data from the next data slots available after the audio data

slots currently in use. Alternatively if required, data may be mapped from any of the available

slots by selection using SPSA bits. The following table shows the default slot mapping for audio

DACs and SPDIF/I

2S data: (further details in the register description section later).

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