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WM8983GEFL/V bảng dữ liệu(PDF) 97 Page - Wolfson Microelectronics plc

tên linh kiện WM8983GEFL/V
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WM8983GEFL/V bảng dữ liệu(HTML) 97 Page - Wolfson Microelectronics plc

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Production Data
WM8983
w
PD Rev 4.0 November 2006
97
REGISTER BITS BY ADDRESS
Notes:
1. Default values of N/A indicate non-latched data bits (e.g. software reset or volume update bits).
2. Register bits marked as "Reserved" should not be changed from the default.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
0 (00h)
[8:0]
RESET
N/A
Software reset
Resetting the
Chip
8
BUFDCOPEN
0
Dedicated buffer for DC level shifting output
stages when in 1.5x gain boost configuration.
0 = Buffer disabled
1 = Buffer enabled (required for 1.5x gain boost)
Analogue
Outputs
7
OUT4MIXEN
0
OUT4 mixer enable
0=disabled
1=enabled
Power
Management
6
OUT3MIXEN
0
OUT3 mixer enable
0=disabled
1=enabled
Power
Management
5
PLLEN
0
PLL enable
0=PLL off
1=PLL on
Master Clock
and Phase
Locked Loop
(PLL)
4
MICBEN
0
Microphone Bias Enable
0 = OFF (high impedance output)
1 = ON
Input Signal
Path
3
BIASEN
0
Analogue amplifier bias control
0=disabled
1=enabled
Power
Management
2
BUFIOEN
0
Unused input/output tie off buffer enable
0=disabled
1=enabled
Power
Management
1 (01h)
1:0
VMIDSEL
00
Reference string impedance to VMID pin
00=off (open circuit)
01=75kΩ
10=300kΩ
11=5kΩ
Power
Management
8
ROUT1EN
0
ROUT1 output enable
0=disabled
1=enabled
Power
Management
7
LOUT1EN
0
LOUT1 output enable
0=disabled
1=enabled
Power
Management
6
SLEEP
0
0 = normal device operation
1 = residual current reduced in device standby
mode
Power
Management
5
BOOSTENR
0
Right channel Input BOOST enable
0 = Boost stage OFF
1 = Boost stage ON
Power
Management
4
BOOSTENL
0
Left channel Input BOOST enable
0 = Boost stage OFF
1 = Boost stage ON
Power
Management
2 (02h)
3
INPPGAENR
0
Right channel input PGA enable
0 = disabled
1 = enabled
Power
Management



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