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WM8983GEFL/V bảng dữ liệu(PDF) 87 Page - Wolfson Microelectronics plc

tên linh kiện WM8983GEFL/V
Giải thích chi tiết về linh kiện  Mobile Multimedia CODEC with 1W Speaker Driver
PDF  123 Pages
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nhà sản xuất  WOLFSON [Wolfson Microelectronics plc]
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WM8983GEFL/V bảng dữ liệu(HTML) 87 Page - Wolfson Microelectronics plc

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Production Data
WM8983
w
PD Rev 4.0 November 2006
87
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
4
PLLPRESCALE
0
0 = MCLK input not divided (default)
1 = Divide MCLK by 2 before input
to PLL
R36
PLL N value
3:0
PLLN
1000
Integer (N) part of PLL input/output
frequency ratio. Use values greater
than 5 and less than 13.
R37
PLL K value
1
5:0
PLLK [23:18]
0Ch
R38
PLL K Value
2
8:0
PLLK [17:9]
093h
R39
PLL K Value
3
8:0
PLLK [8:0]
0E9h
Fractional (K) part of PLL1
input/output frequency ratio (treat as
one 24-digit binary number).
Table 59 PLL Frequency Ratio Control
The PLL performs best when f2 is around 90MHz. Its stability peaks at N=8. Some example settings
are shown in Table 60.
MCLK
(MHz)
(F1)
DESIRED
OUTPUT
(MHz)
F2
(MHz)
PRESCALE
DIVIDE
MCLKDIV
R
PLLN
R36
(Hex)
K
(Hex)
PLLK
[23:18]
R37
(Hex)
PLLK
[17:9]
R38
(Hex)
PLLK
[8:0]
R39
(Hex)
12
11.29
90.3168
1
2
7.5264
7
86C226
21
161
26
12
12.288
98.304
1
2
8.192
8
3126E8
C
93
E9
13
11.29
90.3168
1
2
6.947446
6
F28BD4
3C
145
1D4
13
12.288
98.304
1
2
7.561846
7
8FD525
23
1EA
126
14.4
11.29
90.3168
1
2
6.272
6
45A1CA
11
D0
1CA
14.4
12.288
98.304
1
2
6.826667
6
D3A06E
34
1D0
6D
19.2
11.29
90.3168
2
2
9.408
9
6872AF
1A
39
B0
19.2
12.288
98.304
2
2
10.24
A
3D70A3
F
B8
A3
19.68
11.29
90.3168
2
2
9.178537
9
2DB492
B
DA
92
19.68
12.288
98.304
2
2
9.990243
9
FD809F
3F
C0
9F
19.8
11.29
90.3168
2
2
9.122909
9
1F76F7
7
1BB
F8
19.8
12.288
98.304
2
2
9.929697
9
EE009E
3B
100
9E
24
11.29
90.3168
2
2
7.5264
7
86C226
21
161
26
24
12.288
98.304
2
2
8.192
8
3126E8
C
93
E9
26
11.29
90.3168
2
2
6.947446
6
F28BD4
3C
145
1D4
26
12.288
98.304
2
2
7.561846
7
8FD525
23
1EA
126
27
11.29
90.3168
2
2
6.690133
6
BOAC93
2C
56
94
27
12.288
98.304
2
2
7.281778
7
482296
12
11
96
Table 60 PLL Frequency Examples for Common MCLK Rates
LOOPBACK
Setting the LOOPBACK register bit enables digital loopback. When this bit is set the output data
from the ADC audio interface is fed directly into the DAC data input.



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