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AS7030B bảng dữ liệu(PDF) 113 Page - ams AG

tên linh kiện AS7030B
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nhà sản xuất  AMSCO [ams AG]
Trang chủ  http://www.ams.com
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AS7030B
Functional Description
Datasheet
• PUBLIC
DS000716
• v1-00 • 2020-Jun-10
128
│ 112
I²C Sequential Read: Shows the format of an I²C sequential read access
Sequential Read is the extended form of Random Read, as more than one register-data bytes are
transferred subsequently. In difference to the Random Read, for a sequential read the transferred
register-data bytes are responded by an acknowledge from the master. The number of data bytes
transferred in one sequence is unlimited (consider the behavior of the word-address counter). To
terminate the transmission the master has to send a not-acknowledge following the last data byte and
generate the STOP condition subsequently.
Figure 151:
I²C Current Address Read
I²C Current Address Read: Shows the format of an I²C current address read access.
To keep the access time as small as possible, this format allows a read access without the word
address transfer in advance to the data transfer. The bus is idle and the master issues a START
condition followed by the Device-Read address. Analogous to Random Read, a single byte transfer is
terminated with a not-acknowledge after the 1st register byte. Analogous to Sequential Read an
unlimited number of data bytes can be transferred, where the data bytes has to be responded with an
acknowledge from the master. For termination of the transmission, the master sends a not-
acknowledge following the last data byte and a subsequent STOP condition.
CONTROL (Address 0x00)
Figure 152:
CONTROL Register
Addr: 0x00
CONTROL
Bit
Bit Name
Default
Access
Bit Description
7:5
Not used
0
RW
Not used
4
hs_en
0
RW
Enable I2C high speed
3
Not used
0
RW
Not used
2
clk_def
0
RW
Set the internal system frequency
Programming is only possible if
oscillator is be disable
0: 2 MHz.
1: 1 MHz
S
DW
A
WA
A
N
A
read register
WA++
data
Sr
DR
P
WA++



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