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ES9033Q bảng dữ liệu(PDF) 9 Page - ESS Technology,Inc |
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ES9033Q bảng dữ liệu(HTML) 9 Page - ESS Technology,Inc |
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9 / 103 page  0.3.1 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 ES9033 Datasheet Information 9 Configuration Modes Hardware Mode The ES9033 has 31 pre-configured modes that can be set with external pin configuration. These modes configure the DAC for different input serial data rates and set the DAC muting. These modes are set with pins: • MODE (Pin 3) • HW0 (Pin 22) • HW1 (Pin 21) • HW2 (Pin 19) • MUTE_CTRL (Pin 20) Each hardware mode pin has 4 states: • 0 – Pin directly connected to GND • 1 – Pin directly connected to AVDD • Pull 0 – Pin pulled to GND through 47kΩ resistor • Pull 1 – Pin pulled to AVDD through 47kΩ resistor Design Information Each hardware mode pin can be configured with either a pull-up or pull-down resistor. Therefore, it is important that the pin is configured to allow for the desired hardware modes. Some guidelines include the following: • By placing a pull-down resistor on the MODE pin, the device is limited to hardware modes with DRE. Alternatively, if a pull-up resistor is placed on the MODE pin, the device is limited to non-DRE modes. • By placing a pull-down resistor on the HW2 pin, the device can no longer access modes 8-11 or modes 24-27. Alternatively, if a pull-up resistor is places on the HW2 pin, the device can no longer use LJ Master mode with an external MCLK. • The HW0 and HW1 pins never require a pull up or pull-down resistor. HW2/ MODE AVDD 47k GPIO HW2/ MODE 47k GPIO Pull-up Pull-down Figure 3 - Hardware mode pin configurations |
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