TMS320C32PCMA50 datasheet(22/45 Pages) TI

22 / 45 page

TMS320C32

DIGITAL SIGNAL PROCESSOR

SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

memory-read-cycle and memory-write-cycle timing (STRBx) (see Figure 16 and Figure 17)

’C32 - 40

’C32 - 50

’C32 - 60

UNIT

NO.

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

td(H1L - SL)

Delay time, H1 low to STRBx low

0†

td(H1L - SH)

Delay time, H1 low to STRBx high

0†

td(H1H - RWL)

Delay time, H1 high to R / W low (read)

0†

td(H1L - A)

Delay time, H1 low to A valid

0†

tsu(D)R

Setup time, D valid before H1 low (read)

th(D)R

Hold time, D after H1 low (read)

tsu(RDY)

Setup time, RDY before H1 low

th(RDY)

Hold time, RDY after H1 low

td(H1H - RWH) Delay time, H1 high to R / W high (write)

tv(D)W

Valid time, D after H1 low (write)

th(D)W

Hold time, D after H1 high (write)

td(H1H - A)

Delay time, H1 high to A valid on back-to-back write

cycles

† Assured from characterization but not tested

R/W

RDY

STRBx ‡

‡ STRBx remains low during back-to-back operations.

Figure 16. Memory-Read-Cycle Timing

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