TMS320C32

DIGITAL SIGNAL PROCESSOR

SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

39

POST OFFICE BOX 1443

timing of peripheral pin configured as general-purpose I/O (see Figure 32)

NO

’C32 - 40

’C32 - 50

’C32 - 60

UNIT

NO.

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

92

tsu(GPIOH1L)

Setup time, general-purpose input before H1 low

10

9

8

ns

93

th(GPIOH1L)

Hold time, general-purpose input after H1 low

0

0

0

ns

94

td(GPIOH1H)

Delay time, general-purpose output after H1 high

13

10

8

ns

Peripheral Pin

(see Note A)

H1

H3

94

94

92

93

NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLKx. The modes of these pins are defined by the contents

of internal control registers associated with each peripheral.

Figure 32. Peripheral-Pin General-Purpose I / O Timing

timing of peripheral pin changing from general-purpose output to input mode (see Figure 33)

NO

’C32 - 40

’C32 - 50

’C32 - 60

UNIT

NO.

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

95

th(H1H)

Hold time, after H1 high

13

12

11

ns

96

tsu(GPI0H1L)

Setup time, peripheral pin before H1 low

10

9

8

ns

97

th(GPIOH1L)

Hold time, peripheral pin after H1 low

0

0

0

ns

97

96

95

Value on

Pin Seen

in

Peripheral

Control Register

Synchronizer Delay

Buffers

Go From

Output to Input

Execute Store

of Peripheral

Control

Register

Data Bit

Peripheral Pin

(see Note A)

I/O

Control Bit

H1

H3

Output

Data

Seen

Data Sampled

NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLKx. The modes of these pins are defined by the contents

of internal control registers associated with each peripheral.

Figure 33. Timing of Peripheral Pin Changing From General-Purpose Output to Input-Mode