TMS320C32

DIGITAL SIGNAL PROCESSOR

SPRS027C – JANUARY 1995 – REVISED DECEMBER 1996

38

POST OFFICE BOX 1443

IOSTRB

STRBx

H3

H1

HOLD

HOLDA

(see Note A)

R/W

A

D

80

80

81

82

81

83

85

87

86

88

90

89

91

84

Write Data

85

86

84.1

NOTE A: HOLDA goes low in response to HOLD going low and continues to remain low until one H1 cycle after HOLD goes back high.

Figure 31. HOLD / HOLDA Timing