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RT3624LE bảng dữ liệu(PDF) 45 Page - Richtek Technology Corporation |
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RT3624LE bảng dữ liệu(HTML) 45 Page - Richtek Technology Corporation |
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45 / 48 page ![]() RT3624LE Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation DS3624LE-00 April 2022 www.richtek.com 45 OVP Threshold 350mV VSEN VR_READY VID Down (Slow Slew rate) Indicator 60 μs PWM 0V Figure 24. Over-Voltage Protection Mechanism Under-Voltage Protection When the output voltage is lower than VID-650mV with 3 µs filter time, UVP is triggered and all PWMs are in tri-state to turn off high-side and low-side power MOSFETs. UVP is masked during DVID period and 80 µs after VID settles. The mechanism is illustrated in Figure 25. VID 650mV VSEN UVP Threshold PWM VR_READY Figure 25. Under-Voltage Mechanism All protections are reset only by VCC/VRON toggle. UVP and OCP protections are listed in Table 18. Note that the real filter time also depends on the magnitude of detected signal. The signal magnitude affects analog comparator’s overdrive voltage and output slew rate. The RT3624LE provides protection flag to promptly determine which kind of protections is triggered. As protection happens, VREF is forced to be 1V/1.5V/2V for OVP/UVP/SUM_OCP, respectively. |
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