RT3624LE datasheet(31/48 Pages) RICHTEK

31 / 48 page

RT3624LE

is a registered trademark of Richtek Technology Corporation

DS3624LE-00

April

2022

www.richtek.com

Thermal Monitoring and Indicator

TSEN pin processes two functions of PIN-SETTING

(function setting) and thermal monitoring. After power

on, TSEN has three operation modes: PIN-SETTING,

Pre-Thermal Sense and Thermal Sense Mode. The

corresponding function blocks of the three modes are

shown in Figure 5. In PIN-SETTING Mode, TSEN pin

voltage = 3.2V x R2 / (R1+R2) with VREF = 3.2V and is

coded by ADC and stored in PIN-SETTING register. In

Pre-Thermal Sense Mode, TSEN pin voltage = 0.6V x

R2 / (R1+R2) with VREF = 0.6V and is coded and

stored in Pre-Thermal Register. This part helps

Thermal Sense Mode calculation. In Thermal Sense

Mode, TSEN pin voltage = 0.6V x R2 / (R1+R2) + 80uA

x [(R1//R2)+R3] with VREF = 0.6V and is coded.

Subtracting Pre-Thermal Register code, the result is

stored in Thermal Register. (The corresponding TSEN

voltage = 80

µA x [(R1//R2)+R3] that’s defined as

Thermal Voltage. R3 is the NTC thermistor network to

sense temperature.) NTC thermistor is recommended

to be placed near the MOSFET, the hottest area in the

PCB. Higher temperature causes smaller R3 and lower

TSEN. According to NTC thermistor temperature curve,

design Thermal Voltage v.s Temperature with proper

R3 network to meet Intel temperature zone. 100°C

Thermal Voltage = 80

µA x [(R1//R2)+R3(100°C)] =

1.105V must be required. Controller processes the

TSEN pin voltage to report temperature zone register.

While the TSEN pin voltage is less than 1.105V, the

VR_HOT is pulled low to indicate thermal alert. The

signal is an open-drain signal. Thermal Register data is

updated every 75

µs and averaging interval is 600µs.

The

resistance

accuracy

TSEN

network

recommended to be less than 1% error.

VREF =

3.2V

TSEN

μA

RNTC

PIN-SETTING

ADC

Pre-Thermal

1.105V

VDDIO

Thermal Register

Thermal Sense Mode

VR_HOT

Figure 5. Multi-Function Pin Setting Mechanism for

TSEN

System Input Power Monitoring (PSYS)

The RT3624LE provides PSYS function to monitor total

platform system power and report to the CPU via SVID

interface. The PSYS function can be illustrated as in

Figure 6. PSYS meter measures system input current

and outputs a proportional current signal IPSYS. RPSYS

is designed for the PSYS voltage = 1.6V with maximum

IPSYS for 100% system input power. 1.6V is a full-scale

analog signal for FFh digitized code.

Input Power

Source

PSYS

ʺMeterʺ

RT3624LE

PSYS

CPU

IPSYS

SVID

Analog Current Signal

(Indicates system total

power)

VPSYS

RPSYS

Figure 6. PSYS Function Block Diagram

System Input Voltage Monitoring (VSYS)

The RT3624LE provides optional VSYS function to

monitor system input voltage. The threshold can be set

through

SVID

interface

and

FFh

digitized

code

indicates for 24V input voltage (24V/255 pre code).If

input voltage is lower than critical threshold, controller

asserts VR_HOT .

RT3624LE bảng dữ liệu(PDF) 31 Page - Richtek Technology Corporation

RT3624LE bảng dữ liệu(HTML) 31 Page - Richtek Technology Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

bảng dữ liệu tải về

Link URL