RT3624LE datasheet(41/48 Pages) RICHTEK

41 / 48 page

RT3624LE

is a registered trademark of Richtek Technology Corporation

DS3624LE-00

April

2022

www.richtek.com

ACLL Performance Enhancement

The RT3624LE provides another optional function to

improve undershoot by applying a positive offset at

loading edge. Controller detects the COMP signal and

compares it with steady state. While VCOMP variation

exceeds a threshold, an additional positive offset is

added to the output voltage. The threshold can be set

through PIN-SETTING separately for PS0 and PS1 as

listed in Table 16. The smaller index indicates that the

detection is triggered easily. The positive offset is

related to the compensation.

The ACLL performance enhancement threshold can

approximate to 60mV/

VEA2

VEA1

In PS0, the slew rate of

VRAMP increases when the VCOMP intersects the

positive offset in order to send out another on-time

earlier to improve undershoot. In PS1, except for the

positive offset, an additional 10mV is applied to the

DAC and one pulse of PWM is also forced to turn on

while the function is triggered. The positive offset is

released gradually in about hundred micro-second.

Figure 20 and Figure 21 show undershoot suppression

behavior in PS0 and PS1. For different platform, the

optimized setting is different. The final setting must be

based on actual measurement.

Table 16. PIN-SETTING of Undershoot Suppression

UDS[1:0]

PS0 (Index)

PS1 (Index)

Disable

200

125

200

175

250

150

Load

Trigger UD

PWM

w/ UD

PWM

w/o UD

Figure 20. Undershoot Suppression Behavior in Multi Phase

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