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TAS5036APFCRG4 bảng dữ liệu(PDF) 19 Page - Texas Instruments

tên linh kiện TAS5036APFCRG4
Giải thích chi tiết về linh kiện  Six Channel Digital Audio PWM Processor
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TAS5036APFCRG4 bảng dữ liệu(HTML) 19 Page - Texas Instruments

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Architecture Overview
13
SLES061B—November 2002—Revised January 2004
TAS5036A
23
22
SCLK
32 Clks
LRCLK
Left Channel
24-Bit Mode
9
8
5
4
1
0
MSB
LSB
2-Channel Left-Justified Stereo Input
23
22
32 Clks
LRCLK
Right Channel
9
8
5
4
1
0
MSB
LSB
NOTE: All data presented in 2s complement form with MSB first.
Figure 2−5. Left-Justified 64-Fs Format
22
21
SCLK
24 Clks
LRCLK
Left Channel
19
9
8
1
0
MSB
LSB
2-Channel Left-Justified Stereo Input/Output (24-Bit Transfer Word Size)
3
2
4
20
23
22
21
24 Clks
Right Channel
19
9
8
1
0
MSB
LSB
3
2
4
20
23
5
5
24-Bit Mode
Figure 2−6. Left-Justified 48-Fs Format
2.1.7.3
Right-Justified Timing
Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and
the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 48
or 64 times Fs is used to clock in the data. The first bit of data appears following the eighth bit-clock period
(for 24-bit data) after LRCLK toggles. In RJ mode, the last bit clock before LRCLK transitions always clocks
the LSB of data. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5036A
masks unused leading data bit positions. Master mode only supports a 64 times Fs bit clock.



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