TAS5036APFCRG4 datasheet(18/62 Pages) TI

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Architecture Overview

SLES061B—November 2002—Revised January 2004

TAS5036A

SCLK

32 Clks

LRCLK (Note Reversed Phase)

Left Channel

24-Bit Mode

20-Bit Mode

16-Bit Mode

MSB

LSB

SCLK

32 Clks

Right Channel

MSB

LSB

2-Channel I2S (Philips Format) Stereo Input

Figure 2−3. I2S 64-Fs Format

2-Channel I2S Stereo Input/Output (24-Bit Transfer Word Size)

SCLK

24 Clks

LRCLK

Left Channel

24-Bit Mode

20-Bit Mode

16-Bit Mode

MSB

LSB

SCLK

24 Clks

Right Channel

MSB

LSB

Figure 2−4. I2S 48-Fs Format

2.1.7.2

Left-Justified Timing

Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and the

right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 48 or 64

times Fs is used to clock in the data. The first bit of data appears on the data lines at the same time that LRCLK

toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5036A masks

unused trailing data bit positions. Master mode only supports a 64 times Fs bit clock.

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