TAS5036APFCRG4 datasheet(17/62 Pages) TI

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Architecture Overview

SLES061B—November 2002—Revised January 2004

TAS5036A

2.1.6 DCLK

DCLK is the internal high-frequency clock that is produced by the PLL circuitry from MCLK. The TAS5036A

uses the DCLK to control all internal operations. DCLK is 8 times the speed of MCLK in normal speed mode,

4 times MCLK in double speed, and 2 times MCLK in quad speed. With respect to the I2C addressable

registers, DCLK clock cycles are used to specify interchannel delay and to detect when the MCLK frequency

is drifting. Table 2−4 DCLK shows the relationship between sample rate, MCLK, and DCLK.

Table 2−4. DCLK

(kHz)

MCLK

(MHz)

DCLK

(MHz)

DCLK Period

(ns)

8.1920

65.5360

15.3

44.1

11.2896

90.3168

11.1

12.2880

98.3040

10.2

22.5280

90.1120

11.1

24.5760

98.3040

10.2

192

49.1520

98.3040

10.2

2.1.7 Serial Data Interface

The TAS5036A operates as a slave only/receive only serial data interface in all modes. The TAS5036A has

three PCM serial data interfaces to accept six channels of digital data though the SDIN1, SDIN2, SDIN3 inputs.

The serial audio data is in MSB-first, 2s-complement format.

The serial data interfaces of the TAS5036A can be configured in right-justified, I2S, left-justified, or DSP

modes. This interface supports 32-kHz, 44.1-kHz, 48-kHz, 88-kHz, 96-kHz, 176.4-kHz, and 192-kHz data

sample rates. The serial data interface format is specified using the data interface control register. The

supported word lengths are shown in Table 2−5.

During normal operating conditions if the serial data interface settings change state, an error recovery

sequence is initiated.

Table 2−5. Supported Word Lengths

DATA MODES

WORD

LENGTHS

MOD2

MOD1

MOD0

Right justified, MSB first

I2S

Left justified, MSB first

DSP frame

2.1.7.1

I2S Timing

I2S timing uses LRCLK to define when the data being transmitted is for the left channel or the right channel.

LRCLK is low for the left channel and high for the right channel. A bit clock running at 48 or 64 times Fs is used

to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes state to the first

bit of data on the data lines. The data is written MSB first and is valid on the rising edge of the bit clock. The

TAS5036A masks unused trailing data bit positions. Master mode only supports a 64 times Fs bit clock.

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