UPD17062 datasheet(211/298 Pages) RENESAS

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209

µPD17062

16.4

WAIT REGISTER

The

µPD17062 can set a state in which the serial interface hardware does not operate, even if a shift clock

is input. This state is called wait mode and is set by the wait register.

The wait register consists of four bits; the SIO0WRQ0 flag, which specifies the timing to stop (wait) serial

interface communication, SIO0WRQ1 flag, SIO0NWT flag, which indicates if whether the current state is

waiting, and the SBACK flag, which indicates whether an acknowledgement is returned in two-wire bus mode.

The wait register, mapped to the register file, is manipulated by executing “PEEK” and “POKE” instructions

via the window register.

All flags of the wait register are reset to 0 at power-on reset and when the system clock is stopped by

executing a STOP instruction.

Fig. 16-4

Configuration of Wait Register

16.4.1

SIO0WRQ1 and SIO0WRQ0 (Serial I/O Wait Request) Flag

The SIO0WRQ1 and SIO0WRQ0 flags reserve (specify) the timing at which the serial interface hardware

is forced to wait. The

µPD17062 expands the concept of waiting from slave operations in two-wire bus mode,

to the transmission side in two-wire bus mode and internal clock operations in serial I/O mode.

During wait, the clock counter and the shift clock applied to the presettable shift register are disabled. This

means that, during wait, the clock counter is not updated and the contents of the presettable shift register

are not shifted, even if the level of the shift clock pin changes.

Bit position

Flag name

SBACK

SIO0NWT SIO0WRQ1 SIO0WRQ0

UPD17062 bảng dữ liệu(PDF) 211 Page - Renesas Technology Corp