UPD17062 datasheet(184/298 Pages) RENESAS

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182

µPD17062

14.5.4

Cautions When Supply Voltage Raised

When supply voltage is raised, careful attention must be given to points (1) and (2) below.

(1) When VDD raised from power-on clear voltage

When VDD is raised, it must be raised to 3.5 V or greater, once.

This is shown in Fig. 14-7.

As shown in Fig. 14-7, when a voltage under 3.5 V is applied when VDD is turned on in a program that uses

clock-stop to back up VDD at 2.2 V, for example, the power-on clear signal continues to be output and the

program does not run.

Since the device output port outputs an undefined value, the supply current increases, according to the

situation, reducing the back-up time with a battery considerably.

Fig. 14-7

Caution When VDD Raised

5 V

0 V

Operation stopped

XOUT

VDD

Power-on

clear signal

Timer carry FF

set pulse

3.5 V

2.2 V

Opera-

tion

stopped

Halt state

50 ms

Normal operation

Back-up

Since the values of the output

ports, etc. are undefined during

this period, the current drain

may increase.

During this period,

initialization is per-

formed, then the

clock is stopped.

Power-on reset

Program start

STOP 0000B

Power-on

clear voltage

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