UPD17062 datasheet(115/298 Pages) RENESAS

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µPD17062

11.3.2

Timing Chart at Interrupt Acceptance

Fig. 11-3 shows the timing chart at interrupt acceptance.

Fig. 11-3 (1) shows the timing chart of one interrupt.

The timing chart when an interrupt request flag is set to 1 is shown in (a) of (1). The timing chart when

an interrupt permission flag is set to 1 is shown in (b) of (1).

In both cases, the interrupt is accepted when the interrupt request flag, interrupt enable flip-flop, and

interrupt permission flag are all set.

If the flag or flip-flop that is set satisfies the skip conditions or the conditions for the first instruction cycle

of the MOVT DBF or @AR instruction, the interrupt is accepted after execution of the skipped instruction

(becomes NOP) or the second instruction cycle of the MOVT DBF or @AR instruction.

The interrupt enable flip-flop is set in the instruction cycle after the cycle in which the EI instruction is

executed.

Fig. 11-3 (2) shows the timing chart when two or more interrupts are used.

If all interrupt permission flags are set when two or more interrupts are used, the interrupt with the highest

hardware priority is accepted first. The program can be used to change the interrupt permission flags to

change the hardware priority.

The interrupt cycle shown in Fig. 11-3 is a special cycle in which an interrupt request flag is reset, a vector

address is specified, and the contents of the program counter are saved after an interrupt is accepted. The

time required for an interrupt is equal to the time required for one instruction (2

µs, or 12 µs when the IDC

is operating). See Section 11.4 for details.

Because the interrupt request flag is set to 1 regardless of the EI instruction and interrupt permission flags,

an interrupt request can be identified by detecting an interrupt request flag using the program.

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