UPD6708 datasheet(21/74 Pages) RENESAS

tên linh kiện	UPD6708

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µPD6708

2.5

Bit Format

The IEBus communication frame bit format (concept) is shown in Figure 2-4.

Figure 2-4. IEBus Bit Format (Concept)

Logic “1”: Potential difference between bus lines (BUS+ pin and BUS– pin) is 20 mV or lower (low level).

Logic “0”: Potential difference between bus lines (BUS+ pin and BUS– pin) is 120 mV or higher (high level).

Preparation period:

The first or subsequent low-level (logic “1”) period

Synchronous period: The next high-level (logic “0”) period

Data period:

The period that expresses the bit value (logic “1”: low level; logic “0”: high level)

The synchronous period and data period have approximately the same length.

The IEBus uses bit-by-bit synchronization. The specifications for the total bit time and the periods allocated to the bits

depend on the type of transfer bit, and on whether the unit is the master unit or the slave unit.

Preparation Period Synchronous Period

Data Period

Logic "1"

Logic "0"

Preparation Period Synchronous Period

Data Period

UPD6708 bảng dữ liệu(PDF) 21 Page - Renesas Technology Corp