TAS5036B datasheet(32/56 Pages) TI

32 / 56 page

Serial Control Interface Register Definitions

SLES073—February 2003

TAS5036B

3.1

General Status Register (x00)

Table 3–2. General Status Register (Read Only)

FUNCTION

No volume update is in progress.

Volume update is in progress.

Always 0

Device identification code

Any valid signal is inactive (see status register (X03)) (see Note 1).

No internal errors (all valid signals are high)

NOTE 1: This bit is reset automatically when one or more channels are active.

3.2

Error Status Register (x01)

Table 3–3. Error Status Register

FUNCTION

FS error has occurred

Control pin change has occurred

LRCLK error

MCLK_IN count error

DCLK phase error with respect to MCLK_IN

MCLK_IN phase error with respect to DCLK

PWM timing error

No errors—no control pins changed

NOTE 2: Write 00 hex to clear error indications in Error Status Register.

3.3

System Control Register 0 (x02)

Table 3–4. System Control Register 0

FUNCTION

Normal mode (in slave mode—quad speed detected if MCLK_IN = 128 Fs)

Double speed

Quad speed

Illegal

Use de-emphasis pin controls

Use de-emphasis I2C controls

No de-emphasis

De-emphasis for Fs = 32 kHz

De-emphasis for Fs = 44.1 kHz

De-emphasis for Fs = 48 kHz

16 bit, MSB first; right justified

20 bit, MSB first; right justified

24 bit, MSB first; right justified

16-bit IIS

20-bit IIS

24-bit IIS

16-bit MSB first

16-bit DSP Frame

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