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TAS5036B bảng dữ liệu(PDF) 19 Page - Texas Instruments

tên linh kiện TAS5036B
Giải thích chi tiết về linh kiện  Six Channel Digital Audio PWM Precessor
PDF  56 Pages
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TAS5036B bảng dữ liệu(HTML) 19 Page - Texas Instruments

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Architecture Overview
13
SLES073—February 2003
TAS5036B
22
21
SCLK
24 Clks
LRCLK
Left Channel
19
9
8
1
0
MSB
LSB
2-Channel Left-Justified Stereo Input/Output (24-Bit Transfer Word Size)
3
2
4
20
23
22
21
24 Clks
Right Channel
19
9
8
1
0
MSB
LSB
3
2
4
20
23
5
5
24-Bit Mode
Figure 2–6. Left-Justified 48-Fs Format
2.1.7.3
Right-Justified Timing
Right-justified (RJ) timing uses an LRCLK to define when the data being transmitted is for the left channel and
the right channel. The LRCLK is high for the left channel and low for the right channel. A bit clock running at
48 or 64 times Fs is used to clock in the data. The first bit of data appears on the data 8-bit clock periods (for
24-bit data) after LRCLK toggles. In RJ mode, the last bit clock before LRCLK transitions always clocks the
LSB of data. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5036B masks
unused leading data bit positions. Master mode only supports a 64 times Fs bit clock.
23
22
SCLK
32 Clks
LRCLK
Left Channel
24-Bit Mode
19
18
15
14
1
0
19
18
20-Bit Mode
15
14
1
0
16-Bit Mode
1
0
15
14
MSB
LSB
2-Channel Right-Justified (Sony Format) Stereo Input
NOTE: All data presented in 2s complement form with MSB first.
23
22
32 Clks
Right Channel
19
18
15
14
1
0
19
18
15
14
1
0
1
0
15
14
MSB
LSB
Figure 2–7. Right-Justified 64-Fs Format



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