TAS5036B datasheet(10/56 Pages) TI

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Introduction

SLES073—February 2003

TAS5036B

1.4

Ordering Information

Texas Instruments

Audio Solutions

5036B

PFC

Device Number

Package Type

AVAILABLE OPTIONS

PACKAGE

PLASTIC 80-PIN TQFP

(PFC)

°C to 70°C

TAS5036BPFC

1.5

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

AVDD_OSC

Analog power supply for internal oscillator cells

AVDD_PLL

Analog power supply for PLL

AVSS_OSC

Analog ground for internal oscillator cells

AVSS_PLL

Analog ground for PLL

CLIP

Digital clipping indicator, active low

CS0

I2C serial control chip address select input, active high

DBSPD

Sample rate is double speed (88.2 kHz or 96 kHz), active high

DM_SEL1

De-emphasis select bit 2, 10 = 48 kHz, 11= undefined (none)

DM_SEL2

De-emphasis select bit 1 (0 = none, 01 = 32 kHz, 10 = 44.1 kHz

DVDD

Digital power supply

DVDD_PWM

Digital power supply for PWM

DVDD_RCL

Digital power supply for reclocker

DVSS

33, 76

Digital ground for digital core and most of I/O buffers

DVSS1

10, 38, 39

DIO

Digital ground for digital core and most of I/O buffers

DVSS_PWM

Digital ground for PWM

DVSS_RCL

Digital ground for reclocker

ERR_RCVRY

Error recovery input, active low

LRCLK

DIO

Serial audio data left / right clock (sampling rate clock) (input when M_S = 0; output when M_S = 1)

M_S

Master/slave mode input signal (master = 1, slave = 0)

MCLK_IN

MCLK input, slave mode (or master / double-speed mode)

MCLK_OUT

MCLK output buffered system clock output if M_S = 1; otherwise set to 0

MUTE

Mute input signal, active low (muted signal = 0, normal mode = 1)

N/C

1, 2, 8, 11,

19–23, 40

Not connected

PDN

Power down, active low

PLL_FLT_OUT

PLL external filter

PLL_FLT_RET

PLL external filter (internally connected to AVSS_PLL)

PWM_AM_1

PWM 1 output (differential -); {positive H-bridge side}

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