S32K310 datasheet(6/146 Pages) NXP

6 / 146 page

Xbar (64 bit)

Fabric

1 MB Pflash with ECC

Memory

3 x FlexCAN

all ch support CAN FD

4 x LPUART (LIN)

Network

16 ch FlexIO

Emulating

UART, I2C, SPI

I2S, SENT, PWM

Communication

64 kB Dflash with ECC

128 kB RAM with ECC

Include 96 kB TCM

FXOSC (8-40 MHz)

Memory

OTA ready -

RWW, A/B swap

•

CPU Platform

Single Arm M7

core

Optimized for Real-

time with zero wait

I/D-TCM

•

Motor Control

On-chip motor

control subsystem

Offloading CPU

•

Future Proof Security/OTA

ISO26262 Compliant Safety System

Scalable Arm platform

Optimized for LOW power

Rich Network/Communication Interface

•

Safety

HW redundancy

MBIST/LBIST/Self Test

Clock/Voltage monitor

Centralized error

detection

ASIL B compliant

•

Security

HW accl for AES 256,

RSA 4096, ECC 521

Firmware included,

upgradable

Side-channel physical

protection

Meet Evita Full

function goal

•

Network/

Communication

CAN/CAN FD, LIN

Flexible IO emulation

•

System

FIRC (48 MHz)

CPU Platform

Cortex-M7

120 MHz

FPU, DSP

I-cache

D-cache

Single Core

SIRC (32 KHz)

PLL

12ch DMA

32ch ext. INT/WKUP

4 x LPSPI

2 x LPI2C

Analog/Timers

BCTU (Body Control Trigger Unit)

2 x 24 ch 12 bit ADC

LCU (Logic Control Unit)

2 x 24 ch 16 bit eMIOS Timer

1 x LPCMP

32 bit RTC

Functional Safety

CMU

FCCU

MPU

SWT

EIM/ERM

STCU2

CRC

Security: HSE-B

Cortex-M0+

RAM

XRDC

Access control

Lifecycle

Management

Asymmetric Hardware Accelerators

Symmetric Hardware Accelerators

TRNG/PRNG

Debug/Trace (SWD/JTAG/ETB)

Figure 2. S32K311: ASIL B Single Core 1MB General Purpose MCU

Xbar (64 bit)

Fabric

2 MB Pflash with ECC

Memory

6 x FlexCAN

all ch support CAN FD

8 x LPUART (LIN)

Network

32 ch FlexIO

Emulating

UART, I2C, SPI

I2S, SENT, PWM

Communication

128 kB Dflash with ECC

192 kB RAM with ECC

Include 96 kB TCM

FXOSC (8-40 MHz)

Memory

OTA ready -

RWW, A/B swap

•

CPU Platform

Single Arm M7

core

Optimized for Real-

time with zero wait

I/D-TCM

•

Motor Control

On-chip motor

control subsystem

Offloading CPU

•

Future Proof Security/OTA

ISO26262 Compliant Safety System

Scalable Arm platform

Optimized for LOW power

Rich Network/Communication Interface

•

Safety

HW redundancy

MBIST/LBIST/Self Test

Clock/Voltage monitor

Centralized error

detection

ASIL B compliant

•

Security

HW accl for AES 256,

RSA 4096, ECC 521

Firmware included,

upgradable

Side-channel physical

protection

Meet Evita Full

function goal

•

Network/

Communication

CAN/CAN FD, LIN

Flexible IO emulation

•

System

FIRC (48 MHz)

CPU Platform

Cortex-M7

120 MHz

FPU, DSP

I-cache

D-cache

Single Core

SIRC (32 kHz)

SXOSC (32 kHz)

PLL

12ch DMA

32ch ext. INT/WKUP

4 x LPSPI

2 x LPI2C

Analog/Timers

BCTU (Body Control Trigger Unit)

2 x 24 ch 12 bit ADC

LCU (Logic Control Unit)

2 x 24 ch 16 bit eMIOS Timer

2 x LPCMP

Functional Safety

CMU

FCCU

MPU

SWT

EIM/ERM

STCU2

CRC

Security: HSE-B

Cortex-M0+

RAM

XRDC

Access control

Lifecycle

Management

Asymmetric Hardware Accelerators

Symmetric Hardware Accelerators

TRNG/PRNG

Debug/Trace (SWD/JTAG/ETB)

32-bit RTC

Figure 3. S32K312: ASIL B Single Core 2MB General Purpose MCU

NXP Semiconductors

Block diagram

S32K3xx Data Sheet, Rev. 7, 04/2023

Data Sheet: Technical Data

Preliminary Information

6 / 146

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