S32K310 datasheet(28/146 Pages) NXP

28 / 146 page

Table 8. Boot time, HSE firmware installed (continued)

Symbol

Description

Min

Typ

Max

Unit

Condition

Spec

Number

first instruction of

the application core,

when HSE firmware

is installed.

MHz; HSE_CLK = 120

MHz.

tBOOT_HSE

After a POR event,

amount of time to

execution of the

first instruction of

the application core,

when HSE firmware

is installed.

—

10.91

—

Device running from

PLL (clocking option

A). CORE_CLK = 160

MHz; HSE_CLK = 80

MHz.

—

6.5.4 HSE firmware memory verification time examples

Table 9. HSE firmware memory verification time examples

Symbol

Description

Min

Typ

Max

Unit

Condition

Spec

Number

tCMAC_64KB

Memory verification

of 64 KB of

application firmware,

using AES-128

CMAC cipher.

—

11.3

—

Device running from

FIRC (clocking option

D). CORE_CLK = 48

MHz; HSE_CLK = 48

MHz.

—

tCMAC_1024KB

Memory verification

of 1024 KB of

application firmware,

using AES-128

CMAC cipher.

—

176

—

Device running from

FIRC (clocking option

D). CORE_CLK = 48

MHz; HSE_CLK = 48

MHz.

—

tGMAC_64KB

Memory verification

of 64 KB of

application firmware,

using AES-128

GMAC cipher.

—

3.2

—

Device running from

FIRC (clocking option

D). CORE_CLK = 48

MHz; HSE_CLK = 48

MHz.

—

tGMAC_1024KB

Memory verification

of 1024 KB of

application firmware,

using AES-128

GMAC cipher.

—

46.8

—

Device running from

FIRC (clocking option

D). CORE_CLK = 48

MHz; HSE_CLK = 48

MHz.

—

tHMAC_64KB

Memory verification

of 64 KB of

application firmware,

using AES-128

HMAC cipher.

—

1.74

—

Device running from

FIRC (clocking option

D). CORE_CLK = 48

MHz; HSE_CLK = 48

MHz.

—

tHMAC_1024KB

Memory verification

of 1024 KB of

—

22.87

—

Device running from

FIRC (clocking option

—

Table continues on the next page...

NXP Semiconductors

Power management

S32K3xx Data Sheet, Rev. 7, 04/2023

Data Sheet: Technical Data

Preliminary Information

28 / 146

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