10

COMMERCIALTEMPERATURERANGE

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

SIGNAL DESCRIPTION

MASTER RESET (MRS1, MRS2)

Afterpowerup,aMasterResetoperationmustbeperformedbyproviding

aLOWpulsetoMRS1andMRS2simultaneously. Afterwards,eachofthetwo

FIFO memories of the IDT723624/723634/723644 undergoes a complete

reset by taking its associated Master Reset (MRS1,MRS2) input LOW for at

least four Port A Clock (CLKA) and four Port B Clock (CLKB) LOW-to-HIGH

transitions.TheMasterResetinputscanswitchasynchronouslytotheclocks.

A Master Reset initializes the associated read and write pointers to the first

location of the memory and forces the Full/Input Ready flag (FFA/IRA, FFB/

IRB) LOW, the Empty/Output Ready flag (EFA/ORA, EFB/ORB) LOW, the

Almost-Empty flag (AEA, AEB) LOW, and forces the Almost-Full flag (AFA,

AFB) HIGH. A Master Reset also forces the Mailbox Flag (MBF1, MBF2) of

theparallelmailboxregisterHIGH.AfteraMasterReset,theFIFO’sFull/Input

Ready flag is set HIGH after two write clock cycles. Then the FIFO is ready

to be written to.

ALOW-to-HIGHtransitiononaFlFO1MasterReset(MRS1)inputlatches

thevalueoftheBig-Endian(BE)inputfordeterminingtheorderbywhichbytes

aretransferredthroughPortB.Italsolatchesthevaluesof theFlagSelect(FS0,

FS1) and Serial Programming Mode (SPM) inputs for choosing the Almost-

FullandAlmost-Emptyoffsetprogrammingmethod.

A LOW-to-HIGH transition on a FlFO2 Master Reset (MRS2) clears the

FlagOffsetregistersofFIFO2(X2,Y2).ALOW-to-HIGHtransitionoftheFIFO2

Master Reset (MRS2) together with the FIFO1 Master Reset (MRS1) input

latches the value of the Big-Endian (BE) input for the Port B and also latches

thevaluesof theFlagSelect(FS0,FS1)andSerialProgrammingMode(SPM)

inputs for choosing the Almost-Full and Almost-Empty offset programming

method (for details see Table 1, Flag Programming, and the Programming

oftheAlmost-EmptyandAlmost-Fullflagssection).TherelevantFIFOMaster

Reset timing diagram can be found in Figure 3.

PARTIAL RESET (PRS1, PRS2)

EachofthetwoFIFOmemoriesofthesedevicesundergoesalimitedreset

bytakingitsassociatedPartialReset(PRS1,PRS2)inputLOWforatleastfour

PortAClock(CLKA)andfourPortBClock(CLKB)LOW-to-HIGHtransitions.

The Partial Reset inputs can switch asynchronously to the clocks. A Partial

Reset initializes the internal read and write pointers and forces the Full/Input

Ready flag (FFA/IRA, FFB/IRB) LOW, the Empty/Output Ready flag (EFA/

ORA, EFB/ORB) LOW, the Almost-Empty flag (AEA, AEB) LOW, and the

Almost-Fullflag(AFA,AFB)HIGH.APartialResetalsoforcestheMailboxFlag

(MBF1,MBF2)oftheparallelmailboxregisterHIGH.AfteraPartialReset,the

FIFO’sFull/InputReadyflagissetHIGHaftertwowriteclockcycles.Thenthe

FIFO is ready to be written to.

Whateverflagoffsets,programmingmethod(parallelorserial),andtiming

mode(FWFTorIDTStandardmode)arecurrentlyselectedatthetimeaPartial

Resetisinitiated,thosesettingswillberemainunchangeduponcompletionof

the reset operation. A Partial Reset may be useful in the case where

reprogrammingaFIFOfollowingaMasterResetwouldbeinconvenient.See

Figure 4 for the Partial Reset timing diagram.

BIG-ENDIAN/FIRST WORD FALL THROUGH (BE/FWFT)

— ENDIAN SELECTION

Thisisadualpurposepin.AtthetimeofMasterReset,theBEselectfunction

isactive,permittingachoiceofBigorLittle-Endianbytearrangementfordata

written to or read from Port B. This selection determines the order by which

bytes (or words) of data are transferred through this port. For the following

illustrations,assumethatabyte(orword)bussizehasbeenselectedforPort

B. (Note that when Port B is configured for a long word size, the Big-Endian

function has no application and the BE input is a “don’t care”1.)

A HIGH on the BE/FWFT input when the Master Reset (MRS1 , MRS2)

inputsgofromLOWtoHIGHwillselectaBig-Endianarrangement.Whendata

ismovinginthedirectionfromPortAtoPortB,themostsignificantbyte(word)

ofthelongwordwrittentoPortAwillbereadfromPortBfirst;theleastsignificant

byte(word)ofthelongwordwrittentoPortAwillbereadfromPortBlast.When

data is moving in the direction from Port B to Port A, the byte (word) written to

PortBfirstwillbereadfromPortAasthemostsignificantbyte(word)ofthelong

word;thebyte(word)writtentoPortBlastwillbereadfromPortAastheleast

significant byte (word) of the long word.

A LOW on the BE/FWFT input when the Master Reset (MRS1, MRS2)

inputsgofromLOWtoHIGHwillselectaLittle-Endianarrangement.Whendata

ismovinginthedirectionfromPortAtoPortB,theleastsignificantbyte(word)

ofthelongwordwrittentoPortAwillbereadfromPortBfirst;themostsignificant

byte(word)ofthelongwordwrittentoPortAwillbereadfromPortBlast.When

data is moving in the direction from Port B to Port A, the byte (word) written to

PortBfirstwillbereadfromPortAastheleastsignificantbyte(word)ofthelong

word;thebyte(word)writtentoPortBlastwillbereadfromPortAasthemost

significant byte (word) of the long word. Refer to Figure 2 for an illustration of

the BE function. See Figure 3 (Master Reset) for the Endian select timing

diagram.

— TIMING MODE SELECTION

AfterMasterReset,theFWFTselectfunctionisactive,permittingachoice

between two possible timing modes: IDT Standard mode or First Word Fall

Through(FWFT)mode.OncetheMasterReset(MRS1,MRS2)inputisHIGH,

aHIGHontheBE/FWFTinputduringthenextLOW-to-HIGHtransitionofCLKA

(for FIFO1) and CLKB (for FIFO2) will select IDT Standard mode. This mode

usestheEmptyFlagfunction(EFA,EFB)toindicatewhetherornotthereare

any words present in the FIFO memory. It uses the Full Flag function (FFA,

FFB)toindicatewhetherornottheFIFOmemoryhasanyfreespaceforwriting.

InIDTStandardmode,everywordreadfromtheFIFO,includingthefirst,must

berequestedusingaformalreadoperation.RefertoFigure3(MasterReset)

for a First Word Fall Through select timing diagram.

Once the Master Reset (MRS1, MRS2) input is HIGH, a LOW on the BE/

FWFTinputduringthenextLOW-to-HIGHtransitionofCLKA(forFIFO1)and

CLKB(forFIFO2)willselectFWFTmode.ThismodeusestheOutputReady

function (ORA, ORB) to indicate whether or not there is valid data at the data

outputs(A0-A35orB0-B35).ItalsousestheInputReadyfunction(IRA,IRB)

to indicate whether or not the FIFO memory has any free space for writing. In

the FWFT mode, the first word written to an empty FIFO goes directly to data

outputs,noreadrequestnecessary.Subsequentwordsmustbeaccessedby

NOTE:

1. Either a HIGH or LOW can be applied to a "don't care" input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily "don't care" (along with

unused inputs) must not be left open, rather they must be either HIGH or LOW.