30

COMMERCIALTEMPERATURERANGE

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

Figure 22. FFB Flag Timing and First Available Write when FIFO2 is Full (IDT Standard Mode)

NOTES:

1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge

and rising CLKB edge is less than tSKEW1, then FFB may transition HIGH one CLKB cycle later than shown.

2. If Port B size is word or byte, FFB is set LOW by the last word or byte write of the long word, respectively.

tCLKH

CSA

EFA

MBA

ENA

A0-A35

CLKA

FFB

CLKB

CSB

3270 drw24

W/RB

12

B0-B35

MBB

ENB

tCLK

tCLKH

tCLKL

tENS2

tENH

tA

tSKEW1

tCLK

tCLKL

tENS2

tENS2

tDS

tENH

tENH

tDH

To FIFO2

Previous Word in FIFO2 Output Register

Next Word From FIFO2

LOW

W/

RA

LOW

LOW

HIGH

LOW

LOW

(1)

FIFO2 Full

tWFF

tWFF

Write