8

COMMERCIALTEMPERATURERANGE

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY

VOLTAGE AND OPERATING FREE-AIR TEMPERATURE

Symbol

Parameter

Min.

Max.

Unit

fS

Clock Frequency, CLKA or CLKB

—

66.7

MHz

tCLK

Clock Cycle Time, CLKA or CLKB

15

—

ns

tCLKH

Pulse Duration, CLKA or CLKB HIGH

6

—

ns

tCLKL

Pulse Duration, CLKA and CLKB LOW

6

—

ns

tDS

Setup Time, A0-A35 before CLKA

↑ and B0-B35 before CLKB↑

4—

ns

tENS1

Setup Time, CSA and W/RA before CLKA

↑; CSB and W/RB before CLKB↑

4.5

—

ns

tENS2

Setup Time ENA and MBA before CLKA

↑; ENB and MBB before CLKB↑

4.5

—

ns

tRSTS

Setup Time, MRS1, MRS2, PRS1, or PRS2 LOW before CLKA

↑ or CLKB↑(1)

5—

ns

tFSS

Setup Time, FS0 and FS1 before MRS1 and MRS2 HIGH

7.5

—

ns

tBES

Setup Time, BE/FWFT before MRS1 and MRS2 HIGH

7.5

—

ns

tSPMS

Setup Time, SPM before MRS1 and MRS2 HIGH

7.5

—

ns

tSDS

Setup Time, FS0/SD before CLKA

↑

4—

ns

tSENS

Setup Time, FS1/SEN before CLKA

↑

4—

ns

tFWS

Setup Time, BE/FWFT before CLKA

↑

0—

ns

tDH

Hold Time, A0-A35 after CLKA

↑ and B0-B35 after CLKB↑

1—

ns

tENH

Hold Time, CSA, W/RA, ENA, and MBA after CLKA

↑; CSB, W/RB, ENB, and MBB after CLKB↑

1—

ns

tRSTH

Hold Time, MRS1, MRS2, PRS1 or PRS2 LOW after CLKA

↑ or CLKB↑(1)

4—

ns

tFSH

Hold Time, FS0 and FS1 after MRS1 and MRS2 HIGH

2

—

ns

tBEH

Hold Time, BE/FWFT after MRS1 and MRS2 HIGH

2

—

ns

tSPMH

Hold Time, SPM after MRS1 and MRS2 HIGH

2

—

ns

tSDH

Hold Time, FS0/SD after CLKA

↑

1—

ns

tSENH

Hold Time, FS1/SEN HIGH after CLKA

↑

1—

ns

tSPH

Hold Time, FS1/SEN HIGH after MRS1 and MRS2 HIGH

2

—

ns

tSKEW1(2)

Skew Time between CLKA

↑ and CLKB↑ for EFA/ORA, EFB/ORB, FFA/IRA, and FFB/IRB

7.5

—

ns

tSKEW2(2,3) Skew Time between CLKA

↑ and CLKB↑ for AEA, AEB, AFA, and AFB

12

—

ns

NOTES:

1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.

2. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.

3. Design simulated, not tested.

(Commercial: VCC = 5V ± 10%, TA = 0

°C to +70°C)

Commercial

IDT723624L15

IDT723634L15

IDT723644L15