5

COMMERCIALTEMPERATURERANGE

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

Symbol

Name

I/O

Description

FS1/SEN FlagOffset

I

FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register programming. During Master Reset,

Select1/

FS1/SENandFS0/SD,togetherwithSPM,selecttheflagoffsetprogrammingmethod.Threeoffsetregister

SerialEnable,

programming methods are available: automatically load one of three preset values (8, 16, or 64), parallel load

from Port A, and serial load.

FS0/SD

FlagOffset

I

When serial load is selected for flag offset register programming, FS1/SEN is used as an enable synchronous to

Select0/

the LOW-to-HIGH transition of CLKA. When FS1/SEN is LOW, a rising edge on CLKA load the bit present on

SerialData

FS0/SD into the X and Y registers. The number of bit writes required to program the offset registers is 32 for the

723624, 36 for the 723634, and 40 for the 723644. The first bit write stores the Y1 register MSB and the last bit

write stores the X2 register LSB.

MBA

Port A Mailbox

I

A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When the A0-A35 outputs

Select

are active, a HIGH level on MBA selects data from the mail2 register for output and a LOW level selects FIFO2

outputregisterdataforoutput.

MBB

Port B Mailbox

I

A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the B0-B35 outputs

Select

are active, a HIGH level on MBB selects data from the mail1 register for output and a LOW level selects FIFO1

outputregisterdataforoutput.

MBF1

Mail1Register

O

MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the

Flag

mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when

a Port B read is selected and MBB is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of

FIFO1.

MBF2

Mail2Register

O

MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to the mail2

register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a

Port A read is selected and MBA is HIGH. MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.

MRS1

FIFO1Master

I

A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the Port B

Reset

outputregistertoallzeroes.ALOW-to-HIGHtransitiononMRS1selectstheprogrammingmethod(serialorparallel)

andoneofthreeprogrammableflagdefaultoffsetsforFIFO1andFIFO2.Italso configuresPortBforbussizeand

endianarrangement. FourLOW-to-HIGHtransitionsofCLKAandfourLOW-to-HIGHtransitionsofCLKBmustoccur

while MRS1 is LOW.

MRS2

FIFO2Master

I

A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the Port A

Reset

outputregistertoallzeroes.ALOW-to-HIGHtransitiononMRS2 toggledsimultaneouslywithMRS1,selectsthe

programming method (serial or parallel) and one of the programmable flag default offsets for FIFO2. Four LOW-

to-HIGHtransitionsofCLKAandfourLOW-to-HIGHtransitionsofCLKBmustoccurwhileMRS2isLOW.

PRS1

FIFO1Partial

I

A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the Port B

Reset

output register to all zeroes. During Partial Reset, the currently selected bus size, endian arrangement, program

ming method (serial or parallel), and programmable flag settings are all retained.

PRS2

FIFO2Partial

I

A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the Port A

Reset

output register to all zeroes. During Partial Reset, the currently selected bus size, endian arrangement, program

ming method (serial or parallel), and programmable flag settings are all retained.

SIZE(1)

BusSizeSelect

I

A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin when BM is

HIGH selects word (18-bit) bus size. SIZE works with BM and BE to select the bus size and endian arrangement

for Port B. The level of SIZE must be static throughout device operation.

SPM(1)

SerialProgram-

I

ALOWonthispinselectsserialprogrammingofpartialflagoffsets.AHIGHonthispinselectsparallel

mingMode

programming or default offsets (8, 16, or 64).

W/RA

Port-AWrite/

I

A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to- HIGHtransitionof

ReadSelect

CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH.

W/RB

Port-BWrite/

I

A LOW selects a write operation and a HIGH selects a read operation on Port B for a LOW-to-HIGH transition of

ReadSelect

CLKB. The B0-B35 outputs are in the HIGH impedance state when W/RB is LOW.

PIN DESCRIPTIONS (CONTINUED)

NOTE:

1. BM, SIZE and SPM are not TTL compatible. These inputs should be tied to GND or VCC.