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November 16, 2007

IDT70P9268

Very Low Power 16K x 16 Synchronous Mobile Multimedia Interface (M2I) Dual Port Static RAM

Industrial Temperature Range

Timing Waveform of Non-Mux’d Port Operation with Counter Repeat

NOTES:

1.

CE, UB/LB = VIL.

2. The "Internal Address" is equal to the "External Address" when

ADS = VIL and equals the counter output when ADS = VIH.

3

. No dead cycle exists during CNTRPT operation. A READ or WRITE cycle may be coincidental with the counter CNTRPT cycle: Address loaded by last valid ADS load will be accessed.

4.

CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is written to during this

cycle.

CLK

Data 1

Data 0

Data 3

Data 2

ADS

tSAD

tHAD

tSA

tHA

An

tSA

tHA

An

tSCN

tHCN

WRITE TO ADS ADDRESS An

ADVANCE COUNTER

WRITE TO An+1

ADDRESS

INTERNAL

ADDRESS

CNTEN

DATAIN

R/W

An+1

An+2

An+2

An

An+1

An+2

tSW

tHW

tSRPT

tHRPT

Data 1

Data 0

ADVANCE COUNTER

WRITE TO An+2

HOLD COUNTER

WRITE TO An+2

REPEAT

READ LAST ADS ADDRESS An

ADVANCE COUNTER

READ An+1

ADVANCE

COUNTER

READ An+1

CNTRPT

DATAOUT