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November 16, 2007

DSC 5695/2

Features

◆ True Dual-Ported Memory Cells

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Allows simultaneous access of the same memory location

◆ High per-port throughput performance

–

Industrial: 800 Mbps

◆ Low-Power Operation

–

Active: 15 mA (typ.)

–

Standby: 2 uA (typ.)

◆ Multiplexed address and data I/Os

◆ Counter enable and repeat features

◆ Full synchronous operation on both ports

◆ Separate upper-byte and lower-byte controls for multiplexed bus

and bus matching compatibility

◆ LVTTL-compatible, single 1.8V (+/- 100mV) power supply

◆ Industrial temperature range (-40C to +85C)

◆ Available in a 100-ball fpBGA (fine pitch BGA)

◆ Green parts available, see ordering information

Block Diagram

NOTES:

1. This block diagram depicts operation with the address and data signals mux’d on the right port but not on the left port. If each port is set to operate with the address and data signals

mux’d, then both sides of the block diagram will be the same as the right port pictured above.

16K x 16

MEMORY

ARRAY

CONTROL

LOGIC

SPECIAL FUNCTION

LOGIC

ZZ CONTROL

LOGIC

Address/Data

I/O Control

I/O0R – I/O15R

ADSR

UBR

LBR

CNTENR

CNTRPTR

CER

OER

R/WR

INTR

CLKR

SF0 – SF7

ZZR

SFEN

CLKR

Address/Data

I/O Control

I/O0L – I/O15L

ADSL

UBL

LBL

CNTENL

CNTRPT L

CLKL

A0L – A13L

CEL

OEL

R/WL

INTL

CLKL

ZZL

DATA0L – DATA15L

Addr0L – Addr13L

DATA0R – DATA15R

Addr0R – Addr13R

Datasheet

IDT70P9268

MOBILE MULTIMEDIA INTERFACE (M2I)

VERY LOW POWER 1.8V

16K X 16

SYNCHRONOUS

DUAL-PORT STATIC RAM