THS8083CPZP datasheet(25/61 Pages) TI

25 / 61 page

3–1

3 Register Definition

3.1

I2C Protocol

The THS8083 is a slave I2C device on which both write and read are supported. As shown in the register map, there

are some status control registers that can only be read.

The device can support FAST I2C mode (SCL up to 400 kHz) when the DTO clock is running at over 25 MHz; at lower

DTO frequencies only NORMAL I2C mode (SCL up to 100 kHz) is supported.

To discriminate between write and read operations, the device is addressed at separate device addresses. There is

an automatic internal subaddress increment counter to efficiently write/read multiple bytes in the register map during

one write/read operation. Furthermore, bit1 of the I2C device address is dependent upon the setting of the I2CA pin,

as follows:

If address selecting pin I2CA = 0, then

WRITE address is 40 hex (01000000)

READ address is 41 hex (01000001)

If address selecting pin I2CA = 1, then

WRITE address is 42 hex (01000010)

READ address is 43 hex (01000011)

3.1.1

Write Format

Slave address(w)

Sub-address

Data0

……

Data(N–1)

Start condition

Slave address(w)

0100000 (0x40) if I2CA=0 / 01000010 (0x42) if I2CA=1

Acknowledge, it is generated by THS8083

Subaddress

Subaddress of the 1st register to write, length: 1 byte

Data0

First byte of the data

Data(N–1)

Nth byte of the data

Stop condition

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