THS8083CPZP datasheet(59/61 Pages) TI

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A–1

Appendix A

PLL Formula and Register Settings

If:

F(XTL) = frequency of external crystal or master clock connected to XTL1 input of THS8083

F(VCO) = frequency of THS8083–internal VCO

F(DTO) = frequency of THS8083–internal DTO

F(DTOCLK) = frequency of externally available DTO clock output

F(HS) = frequency of HS input

CLKDIV = clock output divider setting

VCODIV = feedback divider in THS8083–internal analog PLL loop

TERMCNT = feedback divider in THS8083–internal digital PLL loop

DTO_INC = DTO increment (when NOM_INC is programmed, DTO_INC is initialized to NOM_INC)

Then:

F(VCO) = F(XTL) x VCODIV

F(DTO) = 31 x F(VCO) / DTO_INC

F(DTOCLK) = F(DTO) / CLKDIV

AND, if PLL is locked:

F(DTOCLK) = TERMCNT * F(HS)

Summarizing:

DTO_INC = [31xF(XTL)xVCODIV] / [F(DTOCLK)xCLKDIV]

The formats of DTO_INC and NOM_INC:

Both are 33 bit values, consisting of a 6-bit integer and a 27-bit fractional part. So, in hexadecimal notation,

the value is between 00.0000000hex and 3F.7FFFFFFhex. The decimal value of the increment is: <integer

part>.<fractional part interpreted as integer value>x2^(–27).

Due to the architecture of the DTO, to all increment values with an integer part higher than 31, 1 needs to be

added when programming the register.

For example:

Actual increment –> Programmed increment

30.0

–>

30.0

31.0

–>

31.0

32.0

–>

33.0

Additional restrictions:

– CLKDIV should be chosen such that the programmed increment NOM_INC falls within the range [28.62]

Examples:

For generating the XGA@75Hz pixel clock of 78.75 MHz, with F(XTL) = 14.31818 MHz & VCODIV=8:

NOM_INC = [31x14.31818x8]/[78.75x1] = 45.090802

Since this is higher than 31, the programmed value needs to be 46.090802. Converting this to the 6bit.27bit

notation, gives us 2E.0B9F645.

To achieve lock with an incoming HS, TERMCNT is programmed with 1312 (i.e., the total number of pixels

per line in this mode).

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