X40410V8-C datasheet(7/24 Pages) RENESAS

7 / 24 page

X40410, X40411, X40414, X40415

FN8116 Rev 0.00

Page 7 of 24

March 28, 2005

BP: Block Protect Bit (Nonvolatile)

The Block Protect Bit, BP, determines which blocks of

the array are write protected. A write to a protected block

of memory is ignored. The block protect bits will prevent

write operations to half or none of the array.

PUP1, PUP0: Power-up Bits (Nonvolatile)

The Power-up bits, PUP1 and PUP0, determine the

tPURST time delay. The nominal power-up times are

shown in the following table.

WD1, WD0: Watchdog Timer Bits (Nonvolatile)

The bits WD1 and WD0 control the period of the Watch-

dog Timer. The options are shown below.

Writing to the Control Registers

Changing any of the nonvolatile bits of the control and

trickle registers requires the following steps:

– Write a 02H to the Control Register to set the Write

Enable Latch (WEL). This is a volatile operation, so

there is no delay after the write. (Operation preceded

by a start and ended with a stop).

– Write a 06H to the Control Register to set the Register

Write Enable Latch (RWEL) and the WEL bit. This is

also a volatile cycle. The zeros in the data byte are

required. (Operation proceeded by a start and ended

with a stop).

– Write a one byte value to the Control Register that has

all the control bits set to the desired state. The Control

where xy are the WD bits, s isthe BP bit and qr are the

power-up bits. This operation proceeded by a start and

ended with a stop bit. Since this is a nonvolatile write

cycle it will take up to 10ms to

complete. The RWEL bit is reset by this cycle and the

sequence must be repeated to change the nonvolatile

bits again. If bit 2 is set to ‘1’ in this third step (qxys

011r) then the RWEL bit is set, but the WD1, WD0,

PUP1, PUP0, and BP bits remain unchanged. Writing

a second byte to the control register is not allowed.

Doing so aborts the write operation and returns a

NACK.

– A read operation occurring between any of the

previous operations will not interrupt the register write

operation.

– The RWEL bit cannot be reset without writing to the

nonvolatile control bits in the control register, power

cycling the device or attempting a write to a write pro-

tected block.

To illustrate, a sequence of writes to the device consist-

ing of [02H, 06H, 02H] will reset all of the nonvolatile bits

in the Control Register to 0. A sequence of [02H, 06H,

06H] will leave the nonvolatile bits unchanged and the

RWEL bit remains set.

FAULT DETECTION REGISTER

The Fault Detection Register (FDR) provides the user

the status of what causes the system reset active. The

Manual Reset Fail, Watchdog Timer Fail and three Low

Voltage Fail bits are volatile.

The FDR is accessed with a special preamble in the

slave byte (1011) and is located at address 0FFh. It can

only be modified by performing a byte write operation

directly to the address of the register and only one data

byte is allowed for each register write operation.

There is no need to set the WEL or RWEL in the control

Protected Addresses

(Size)

Array Lock

None

100h – 1FFh (256 bytes)

Upper Half of

Memory Array

PUP1 PUP0

Power-on Reset Delay (tPURST)

50ms

200ms (factory setting)

400ms

800ms

WD1

WD0

Watchdog Time Out Period

1.4 seconds

200 milliseconds

25 milliseconds

disabled (factory setting)

6543

LV1F LV2F

WDF

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